Principal Digital & Mixed-Signal IC Design Engineer

Oso Semiconductor

• $162K — $195K *
Telecommunications & Hardware
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • 5-10 years of experience in digital and mixed-signal IC design
  • Proficient in RTL design and verification with strong knowledge of VHDL/Verilog
  • Deep understanding of analog design principles and circuit characteristics
  • Experience with complex systems involving multi-channel RF front ends
  • Familiarity with calibration techniques and data converters

Responsibilities

  • Lead the design of control, interface, and calibration circuitry for beamformer ICs
  • Develop digital logic and mixed-signal blocks for multi-channel RF systems
  • Collaborate with cross-functional teams including RFIC and layout engineers
  • Drive the design process from architecture through verification to silicon bring-up
  • Implement built-in test functions for on-chip monitoring and performance validation

Benefits

  • Opportunity to work on cutting-edge technology in RF and mixed-signal IC design
  • Potential for professional growth in a senior technical leadership role
  • Collaborative environment with a focus on innovation and team input
  • Access to state-of-the-art tools and resources for design and testing
  • Flexible work environment with potential remote work opportunities
Full Job Description
We're looking for a Principal Digital & Mixed-Signal IC Design Engineer to own the control, interface, calibration, monitoring, and mixed-signal support circuitry in our next-generation beamformer ICs. You'll develop digital logic and mixed-signal blocks that configure and monitor multi-channel RF front ends, from serial interfaces and register maps through on-chip sensors, data converters, and built-in test functions. This is a senior hands-on design role spanning RTL and transistor-level analog/mixed-signal design. You'll work closely with RFIC, systems, test, and layout engineers to build robust digital control and observability into our chips and take those functions from architecture through verification, tapeout, and silicon bring-up.

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