Astera Labs

Principal Digital Design Engineer

Astera Labs • $120K — $150K *
Toronto, ON M3C 0E3In-Person
Telecommunications & Hardware
8 - 10 years of experience
Today
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Job Overview by Ladders

Qualifications

  • Bachelor's in Electronics/Electrical engineering (Master's preferred)
  • 8+ years of digital design experience with 4+ years in PCIE or Ethernet controller, PCS or PHY implementation
  • Expertise in RTL development and synthesis, particularly in timing closure
  • Experience with front-end design and gate-level simulations
  • Strong proficiency in System Verilog/Verilog and scripting languages like Python/Perl

Responsibilities

  • Design and implement high-performance digital solutions, including RTL development and synthesis
  • Collaborate with cross-functional teams on IP integration for Serdes and Controller IPS, processors, and peripherals
  • Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ? 16nm
  • Ensure timing closure and assess verification completeness, including CDC and lint checks
  • Utilize design and emulation tools from Synopsys/Cadence

Benefits

  • Opportunities for professional growth and advancement
  • Collaborative and innovative work environment
  • Access to advanced design tools and technologies
  • Engagement in cutting-edge connectivity solutions development
Full Job Description
Job Description

We are seeking a Principal Digital Design Engineer with deep expertise in high-performance PCIE or Ethernet controller and bridge or switch design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions.

Key Responsibilities:
  • Design and implement high-performance digital solutions, including RTL development and synthesis.
  • Collaborate with cross-functional teams on IP integration for Serdes and Controller IPS, processor and peripherals
  • Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes 6#8804; 16nm.
  • Ensure timing closure, assess verification completeness, CDC, lint etc.
  • Utilize tools from Synopsys/Cadence for design and emulation.

Basic Qualifications:
  • Bachelor6#39;s in Electronics/Electrical engineering (Master6#39;s preferred).
  • +8 years of digital design experience, with 4+ years focused on PCIE or Ethernet controller, PCS or PHY implementation.
  • Proven expertise in RTL development, synthesis, and timing closure.
  • Experience with front-end design, gate-level simulations, and design verification.
  • Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.

Required Expertise:
  • Hands-on experience with PCIE or Ethernet Controller or Serdes/PHY IP.
  • Hands-on pre-silicon and post-silicon design implementation.
  • Hands-on experience FW interaction and embedded design.
  • Strong proficiency in System Verilog/Verilog and scripting (Python/Perl).
  • Experience with block-level and full-chip design at advanced nodes (6#8804; 16nm).
  • Top level integration and DFT knowledge.

Preferred Experience:
  • PCIE or Ethernet SerDes controller or IP level experience.
  • Understanding of PAD design, DFT, and floor planning.
  • Experience with NIC, switch, or storage product development including embedded FW.
  • Familiarity with working in design and verification workflows in a CI/CD environment.

About Astera Labs

Astera Labs is a semiconductor company that designs and develops purpose-built connectivity solutions for data-centric systems. The company's portfolio of products includes system-aware semiconductor integrated circuits (ICs), boards, and intellectual property (IP) that are used in data center servers, storage, and networking equipment. Astera Labs' products are designed to improve the performance, latency, and power consumption of data-centric systems. The company was founded in 2018 and is headquartered in Santa Clara, California.
Learn more about Astera Labs
Size
51 employees
Industry
Manufacturing & Automotive
Net Income
-$3 million
Founded
2018
Revenue
$5 million
NASDAQ
ALAB
* Ladders Estimates
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