Job DescriptionWe are looking for
Principal Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.
Basic Qualifications:- Strong academic and technical background in electrical engineering. A Bachelor's degree in EE is required, and a Master's degree is preferred.
- +8 years' experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
- Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
- Authorized to work in the US and start immediately.
Required Experience:- Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
- Proven front end design expertise - architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
- Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production
- Experience with Synopsys and/or Cadence digital design tools/flows
- Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
- Familiarity with UVM based design verification
- Silicon bring-up and debug expertise
- Small-geometry CMOS (6428nm) design
Preferred Experience:- Firmware development with C-language, scripting with Python or other equivalent programming languages.
- Development/support for PCIe or Ethernet Switch products.
The base salary range is $185,000.00 USD - $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
