Principal application Engineer – Digital Implementation & Physical Design

Location: Malaysia

Job Overview

We are seeking a Principal application Engineer to support and drive the adoption of Cadence’s digital implementation, physical design, and static verification solutions across key customers in the region.

In this role, you will combine deep hands-on physical design expertise with technical leadership and customer engagement, helping customers achieve optimal performance, power, and area (PPA) on advanced technology nodes. You will work closely with customer design teams, Cadence R&D, Product Engineering influencing methodologies and ensuring successful project execution and tool adoption.

•The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure

The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high-speed designs at the latest technology nodes.

The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.

The candidate will work closely with RTL design team to ensure successful tapeouts.

Requirement:

BS/MS in EE/CS with 7+ years of hands-on experience in physical design and verification with prior working experience in 7nm and below technologies.

Experienced with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology issues.

Solid knowledge on Low Power Design

Able to assume responsibility for a variety of technical tasks and to work independently

Self-motivated, able to work as a team player, and good English communication skills