Advanced Micro Devices, Inc

Power Analysis and Optimization Engineer

Advanced Micro Devices, Inc$120K — $150K *
Consumer Technology
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Solid background in SoC design with expertise in power reduction techniques.
  • Proficiency in interpreting power estimation tools for optimization strategies.
  • Strong analytical and problem-solving skills.
  • Excellent communication abilities in a collaborative setting.
  • Bachelor's or master's degree in electrical or computer engineering.

Responsibilities

  • Understand and establish power requirements, creating strategies to meet them.
  • Periodically report design status to stakeholders.
  • Perform detailed power estimation and analyze results to identify improvements.
  • Drive comprehensive power analysis and optimization for SoCs and IP blocks.
  • Implement low-power design strategies effectively.
  • Create power domains and islands using UPF methodology.
  • Develop robust power analysis flows utilizing industry-standard EDA tools.
  • Correlate RTL power estimates with gate-level and post-layout results.
  • Contribute to the evolution of SoC design methodologies for future projects.

Benefits

  • Comprehensive AMD employee benefits package.
Full Job Description
THE ROLE:

AMD-Xilinx is seeking a capable and motivated SoC Design Engineer to be part of Front-End SoC Design Team. In this role, you will focus on power analysis and optimization to help design high performance and power efficient SoCs.

THE PERSON:
  • The ideal candidate should have a solid background in SoC design with strong knowledge of power reduction techniques.
  • You should be proficient in interpreting results from power estimation tools and translating them into effective power optimization strategies.
  • The candidate should demonstrate strong analytical thinking and problem-solving abilities.
  • Excellent communication skills, along with the ability to work effectively in a collaborative, team-oriented environment.

KEY RESPONSIBILITIES:
  • Understand power requirements, establish the baseline, create a strategy to meet requirements, monitor the evolution of the design, and guide the team towards meeting power requirements.
  • Report status periodically to stake holders.
  • Perform vector-based and vector-less power estimation for different use case scenarios and analyze results to identify areas for improvement.
  • Drive static and dynamic power analysis and optimization for complex SoCs and IP blocks.
  • Drive low-power design strategies.
  • Power domain/island creation (with UPF).
  • Develop and maintain power analysis flows using industry-standard EDA tools and emerging, cutting-edge methodologies.
  • Correlate RTL power estimates with gate-level and post-layout power results.
  • Contribute to definition/evolution of SoC Design methodologies and processes for future projects.

PREFERRED EXPERIENCE:
  • A successful candidate will have an SoC/ASIC design background, would have participated in several silicon design projects with increasing level of scope/responsibilities in managing power optimization through the project life cycle.
  • Expertise with low-power design methodologies and trade-offs.
  • Hands-on expertise with EDA tools such as PrimeTime, PrimePower, Power Artist.
  • Experience with RTL design and analysis (Verilog/System Verilog).
  • Experience designing with multiple power domains and islands using UPF.
  • TCL, Python, Perl scripting, familiarity with AI tools such as Claude, Codex.

ACADEMIC CREDENTIALS:
  • Bachelor's or master's degree in electrical or computer engineering.

LOCATION: San Jose, CA

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

About Advanced Micro Devices, Inc

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ

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