Advanced Micro Devices, Inc

Mixed Signal Custom Layout Engineer (1-Year Temporary)

Advanced Micro Devices, Inc • $80K — $120K *
Markham, ON L3R 0G6In-Person
Technical Services
Less than 5 years of experience
Today
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Job Overview by Ladders

Qualifications

  • 2-3 years of experience in custom layout design preferred
  • Strong understanding of CMOS device/circuit theory
  • Proficiency with industry-standard layout tools like Virtuoso and Calibre
  • Experience with LVS, DRC, EMIR, and other physical verification flows
  • Exposure to advanced semiconductor nodes (2nm/3nm) and familiarity with 5nm/7nm technology
  • Background in high-speed signaling, PLL/DLL/VCO, DACs, and power pads
  • Scripting/automation skills in Perl, TCL, SVRF, TVF, or SKILL are a plus

Responsibilities

  • Create clean, robust layouts for digital and analog building blocks in Cadence Virtuoso
  • Floorplan, route, and assemble lower-level cells into macros
  • Build black-box models and views for other teams' consumption
  • Run hierarchical checks (DRC, LVS, ERC, EM/IR, Latch-up/ESD) and iterate with circuit owners
  • Leverage AI-assisted tools for layout productivity and design quality

Benefits

  • Comprehensive AMD benefits package
  • Flexible working arrangements
  • Opportunity for professional development
  • Access to cutting-edge technology and projects
  • Collaborative work environment with top industry talent
Full Job Description
Responsibilities

THE ROLE:

The full custom IC layout group is looking for a candidate to design the layout for digital and analog circuits based on schematics using industry leading CAD tools and cutting edge foundry technology. Examples of layout designed by our team include Phase Locked Loop (PLL), Delay Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High Speed Differential Signaling circuitry, Droop Detect, and Die Crack Monitor. Proficiency in 2D layout design while being able to visualize in 3D space are traits ideal for this position. It is useful to have knowledge of digital and analog circuitry at the CMOS transistor level.

THE PERSON:

The candidate will be able to see through the different stages of a project development - from initial floor planning and routing of low level logic gates through top level integration of numerous blocks and ultimately, project tape out related tasks. Day to day responsibilities include layout of lower level cells and assembly of these lower level cells into IPs. You will be running various verification tools at all levels of the design hierarchy. These include DRC, LVS, EM/IR, ERC and Latch up/ESD. Over time, responsibilities will expand to include guiding and coordinating off-shore contractors performing layout tasks.

KEY RESPONSIBILTIES:
  • Create clean, robust layouts for digital and analog building blocks at the transistor level in Cadence Virtuoso.
  • Floorplan, route, and assemble lower-level cells into macros
  • Build black-box/abstract models and views consumed by other teams; contribute to tapeout collateral for custom blocks.
  • Run hierarchical checks at cell/macro levels (DRC, LVS, ERC, EM/IR, Latch-up/ESD) and iterate to closure in partnership with circuit owners.
  • Explore and leverage AI-assisted tools and workflows to improve layout productivity, verification efficiency, and design quality.

This team is essential to the success of AMD as a cutting edge company. You will be working on some of the most exciting projects the industry has to offer. It is a very exciting environment and you will be working with the very best in our technology.

PREFERRED EXPERIENCE:
  • 2-3 years of experience in custom layout design is preferred
  • Strong understanding of CMOS device/circuit theory and analog/digital layout best practices.
  • Proficiency with industry-standard layout tools (e.g., Virtuoso, Calibre)
  • Experience with LVS, DRC, EMIR and other physical verification flows
  • Exposure to advanced nodes (e.g., 2nm/3nm; experience at 5nm/7nm also valued).
  • Background with IP/standard-cell layout, high-speed differential signaling, PLL/DLL/VCO, DACs, power pads, and in-context XOR.
  • Scripting/automation in Perl, TCL, SVRF/TVF, SKILL is a plus


ACADEMIC CREDENTIALS:

Electrical/Mechanical Engineering Degree and/or Electronics related Diploma

#LI-CC4

Qualifications

Benefits offered are described: AMD benefits at a glance.

About Advanced Micro Devices, Inc

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Manufacturing & Automotive
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ
AMD
* Ladders Estimates

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