Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in physical design, including custom structured datapath implementation.
- Experience hardening dense compute units (such as dot-product engines, multiplier-accumulator (MACs), multipliers, or arithmetic logic unit (ALUs) into high-frequency, low-power macros.
- Experience in sub-7nm process nodes (including FinFET and Gate-All-Around architectures), managing the physical density and routing congestion typical of custom datapaths.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with focus on computer architecture.
- Experience in structured placement methodologies (e.g., relative placement, data-flow driven layout, and customized power-grid stitching for dense blocks).
- Experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation.
- Experience with physical design and timing, with managing PT-to-PnR timing correlations and metal-fill impacts on dense structures.
- Expert-level scripting versatility (Tcl, Python, Perl) to build layout automation and structural constraints within standard EDA tools.
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will be empowering Google and our customers with breakthrough capabilities by delivering transformational, co-optimized silicon and technology leadership at scale.
Responsibilities- Own critical custom datapath and matrix multiplication accumulator blocks, driving execution from RTL-to-GDSII including synthesis, floor-planning, place and route (PNR), timing closure, and physical signoff.
- Understand math-intensive micro-architecture to perform detailed feasibility studies, analyzing performance, power, and area (PPA) tradeoffs to achieve optimal design closure.
- Develop and improve advanced physical design methodologies and customize implementation recipes, specifically optimizing PPA across complex arithmetic pipeline structures. Manage different PNR tools - synopsys fusion compiler, cadence (Innovus/Genus), PrimeTime, StarRC, Calibre, Apache Redhawk.
- Implement and execute key design phases: floor-planning, synthesis, placement, clock tree synthesis (CTS), timing closure, routing, extraction, physical verification (design rule checking (DRC)/layout versus schematic (LVS), electromigration (EM)/IR, and final signoff.
- Lead sub-chip execution and drive delivery, providing direct technical guidance and mentorship to a small team of engineers to ensure on-schedule project completion.
US: $192000 - $278000 (USD) 20% bonus target equity benefits
Learn more about benefits at Google .
