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X In most instances, this position requires in-person interviews as part of the hiring process.
Minimum qualifications: - Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 4 years of experience in physical design.
- Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
- Experience in high-performance synthesis, PnR, sign-off convergence, including STA and sign-off optimizations.
Preferred qualifications: - Experience in top-level floorplanning and block integration.
- Experience in low power design implementation including UPF/CPF, multi-voltage domains and power gating.
- Experience with ASIC design flows and methodology of physical design.
- Understanding of circuit design, device physics, and deep submicron technology.
- Knowledge of Verilog/SystemVerilog and fundamentals of computer architecture.
- Effective skills with scripting languages such as Tcl, or Perl.
Responsibilities - Develop all aspects of ASIC RTL2GDS implementation for high Performance, Power, Area (PPA) designs.
- Manage full-chip level physical implementation.
- Define and implement innovative schemes to improve performance and power.
- Work with cross-functional teams to deliver best quality of results.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $197000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
