Job Details:

Job Description: 
As a Network Platform Architect, you will be at the forefront of defining, building, and securing Intel's network strategy, playing a pivotal role in creating the backbone that supports our cutting-edge technologies. This role is critical in driving architectural reviews, solving complex network challenges, and delivering secure and efficient infrastructure to meet the evolving needs of Intel's business. In this role you will define the platform integration and adapter architecture end-to-end for our networking products. The role will have significant collaboration with partners and customers to ensure you stay up to date with latest trends and technologies around connectivity, manageability, cooling, form factor etc. The role is critical in the definition of our next generation products. This role sits at the intersection of SoC architecture, board design, platform firmware/software, and OEM/ODM integration, ensuring that silicon capabilities translate into deployable, serviceable, and scalable adapter solutions. You will drive platform-level requirements and architecture closure early, aligning SoC capabilities with adapter constraints, customer/OEM expectations, and data center operational needs. Your expertise in network design, telemetry, monitoring and security will empower innovation across cloud technologies, analytics, AI, data centers, and more, ensuring that Intel remains a leader in the technology landscape. 1) IPU/DPU/NIC Card / Adapter Architecture Ownership Define the adapter card architecture for IPU-based NIC products, including form factor, I/O topology, feature partitioning (SoC vs board), and platform integration requirements. Own the board-level architecture: PCIe connectivity assumptions, retimer/redriver strategy, clocking/reset strategy, SPI/I2C/SMBus/USB topology, secure boot/update and debug hooks as they relate to the card. Drive system partitioning tradeoffs: what must live in SOC vs what can be implemented on-card (PHY topology options, management sideband bridging, sensors/FRU, etc.). Author and maintain platform architecture artifacts (adapter architecture spec, block diagrams, interface requirements, bring-up requirements, OEM integration guide). Lead cross-functional architecture reviews with silicon, board, FW/SW, validation, and manufacturing teams to ensure adapter design meets platform requirements. 2) Platform Manageability Interconnect and Serviceability Architecture Define the platform manageability architecture for the adapter across OEM variants, including: Sideband/manageability interface requirements and minimum viable feature set definition. Management traffic separation strategy (data-plane vs management-plane considerations) and platform integration constraints. Drive requirements and architectural decisions for manageability interconnect options (e.g., board-level vs SoC-level scope and ownership boundaries). Ensure the manageability solution supports operational needs: inventory, sensor/telemetry exposure, secure device identity, firmware lifecycle hooks, and platform compatibility constraints (including OEM differences). Coordinate with FW/SW teams to ensure manageability requirements are reflected consistently in requirements and translated into implementable roadmaps. 3) Platform Thermal, Power, and Reliability Requirements Own the adapter-level thermal and power envelope definition: Establish card power targets (typical/peak/transient), power states, and throttling/derating assumptions. Define cooling assumptions (airflow class, heatsink constraints, chassis limitations) and coordinate with mechanical/thermal engineering to close feasibility. Drive power delivery architecture requirements: VR selection strategy, rail budgeting, margin methodology, inrush/steady-state considerations, and platform constraints alignment. Define platform-level reliability and serviceability expectations: sensor placement/coverage expectations, fault containment, diagnostics/debug hooks, and service workflows. 4) Cross-Functional Leadership and Execution Serve as the single platform architecture voice connecting SoC architecture decisions with adapter constraints and OEM deployment realities (ensuring proactive alignment vs reactive late-cycle changes). Lead technical alignment across silicon architecture, board design, FW/SW, validation, and operations stakeholders to drive closure on platform-level risks. Partner with product/program leadership to define platform milestones, gating criteria, and review readiness for customer/OEM engagements.

Qualifications:
Minimum Qualifications 8+ years' experience in one or more of: NIC/adapter platform architecture, server platform architecture, SoC-to-board integration, or high-speed I/O platform design. Demonstrated experience defining adapter/card architectures that balance electrical, thermal, mechanical, cost, and manufacturability constraints. Strong understanding of platform manageability concepts and sideband integration constraints across OEM environments (requirements definition, MVP scoping, compatibility tradeoffs). Experience defining and closing thermal/power envelopes for add-in cards or tightly constrained platforms (including working with thermal/mechanical engineering and validation). Proven ability to drive cross-functional alignment and deliver architecture specifications that teams can execute against. Bachelor's degree in computer science, Network Engineering, or a related field, or equivalent experience in line with business needs. Preferred Qualifications Experience with hyperscale/OEM deployment constraints for adapter cards (serviceability, telemetry expectations, fleet operations patterns). Expertise in high-speed I/O and Ethernet NIC platforms (signal integrity tradeoffs, system bring-up realities, platform-level debug). Prior leadership owning platform readiness across multiple SKUs or OEM variants (balancing commonality vs forks). Familiarity with translating requirements into phased implementation plans under resource constraints. Strong problem-solving skills with a focus on delivering innovative and scalable solutions. Excellent communication skills to effectively collaborate with cross-functional teams and stakeholders. Proven ability to navigate complex business processes and translate them into actionable network strategies. Passion for staying abreast of emerging technologies and security trends. Embark on a career with Intel where you'll have the opportunity to shape the future of networking and security. Apply today to join a team that empowers innovation and delivers impactful solutions to the world's toughest challenges.

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations:US, Arizona, Phoenix, US, Oregon, Hillsboro, US, Texas, Austin

Business group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

 

 

Annual Salary Range for jobs which could be performed in the US: $203,200.00-286,870.00 USD

 

 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

 

 

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*