Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:Job Overview:- Design adaptive power management controller, on-chip sensor controller and digital power meter.
- Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks.
- Work closely with technology/circuit design team to close IP block specification/requirement.
- Work closely with verification/physical design team to complete the IP design implementation.
- Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows.
- Work closely with system/software/test team to enable the low power feature in wireless SoC product.
- Work closely with system/software/test team to enable functional safety feature in automotive SoC product.
- Create/Enhance low power methodologies covering entire design cycle from RTL to GDS. Analyze how a new methodology will affect different phases of the design/verification cycle and work on fixing any issues.
- Provide feedback for low-power chip and system architecture.
- Understand and perform block & chip-level power analysis.
- Understand and create block-level power models.
Required for this Role:
- 3 years of experience doing low power digital ASIC design.
- Familiar with ASIC front-end design process and related flow, including u-arch, RTL coding, simulation, synthesis, STA.
- Familiar with scripting languages like Python, Perl, TCL
- Understanding of electrical engineering concepts, circuit analysis and logic design skills.
Preferred Qualifications:- Previous experience in AVS (adaptive voltage scaling) desired.
- Familiarity with advanced low power techniques and tools such as UPF, CLP, power aware DV and high speed clocking desired.
- Proficiency in Verilog/System Verilog coding, verification techniques, and scripting language, such as: Perl, Python, Tcl, and Make etc.
- Good understanding of SoC architecture/micro-architecture.
- Understanding of automotive functional safety standard ISO 26262 and analysis technique (FMEA/FMEDA) is a plus.
- Strong debugging capabilities at simulation, emulation, and Silicon environments, including ability to design interesting debug experiments.
- Collaborate closely with cross-function team to research, design and implement performance and power management strategy for product roadmap.
Education: - Masters or PhD in Electrical or Computer Engineering
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
Pay range and Other Compensation & Benefits: $115,600.00 - $173,400.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
