General Summary:In this position, you will be responsible for RTL design and verification of digital IPs used across the board in Qualcomm chips. You will have the opportunity to work on critical high-speed clock IPs, power-sequencing blocks integral to Qualcomm's low power designs, custom FIFOs and high-speed latch arrays. The position also involves close collaboration with SOC design and verification teams on specification, integration, development, and support of front-end deliverables for these Soft/Hard-Macros.
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
Qualifications:
The ideal candidate would possess the following qualifications:
- Master's degree in science, Engineering or related field
- 2+ years of professional or academic experience with RTL design or verification of digital IPs
- Design verification knowledge and experience with design testbench suites.
- Good understanding of OOP concepts. Experience in HVL such as System Verilog, UVM/OVM & System C
- Familiarity with Power-aware Verification is a plus
- Good working knowledge of synthesis and STA
- Knowledge of low power design techniques
- Ability to work with transistor-level circuit designers
- Familiarity with ASIC backend integration tools for PNR is a plus
- Familiarity with IP delivery collaterals including behavior model, upf libs, LEF view, etc is a plus
- Automation knowledge (python) etc. will be a significant plus
Required for this role:
- Education: Bachelors - Electrical Engineering, Bachelors - Science
- Work Experiences: 2+ years ASIC design, verification, or related work experience
- Should be able to use simulation and formal verification methodologies to execute test plans, write checkers, assertions and develop stimulus.
- Strong knowledge in digital logic design (Data path and Finite Sate Machine (FSM) Design)
- Skills: Verilog, System Verilog, Perl, Circuit Design
Pay range and Other Compensation & Benefits: $115,600.00 - $173,400.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
