USM Business Systems

JB061568 - Lead ASIC DFT Engineer

USM Business Systems • $120K — $160K *
San Jose, CA 95123In-Person
Telecommunications & Hardware
Less than 5 years of experience
Yesterday
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Job Overview by Ladders

Qualifications

  • 5-7 years of hands-on experience in ASIC DFT with end-to-end ownership.
  • Strong understanding of DFT fundamentals, including fault models and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, and silicon debug techniques.
  • Practical experience with industry-standard EDA tools (Synopsys, Cadence, Mentor).
  • Proven skills in scan insertion, ATPG setup, simulation, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS background preferred.
  • Familiarity with scan chain stitching and related tools like Tessent.

Responsibilities

  • Lead DFT implementation from inception to completion.
  • Design and optimize test strategies for fault coverage and efficiency.
  • Collaborate with cross-functional teams on DFT integration and verification efforts.
  • Perform comprehensive debug and validation of DFT solutions in silicon.
  • Generate and maintain documentation for DFT processes and results.
  • Participate in discussions for design architecture and enhancements regarding DFT capabilities.

Benefits

  • Opportunities for professional growth and development in a cutting-edge technology environment.
  • Collaborative work culture with top-tier engineers and innovative projects.
  • Access to state-of-the-art tools and technologies in ASIC design.
  • Support for skill enhancement through training and workshops.
Full Job Description
  • Start Date: Interview Types
  • Skills ASIC DFT, Visa Types Green Card, US Citiz..


    • Required Skills & Qualifications

    • Strong hands-on experience in ASIC DFT with end-to-end ownership.
    • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
    • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
    • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
    • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
    • Experience with MBIST implementation and verification; SMS experience preferred.
    • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
    • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
    • Proven post-silicon debug and silicon bring-up experience.
    • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
    • Strong communication skills and the ability to work independently with minimal ramp-up.


    Preferred Experience

    • MBIST post-silicon validation.
    • ATPG simulations and fault coverage debug.
    • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
    • DFT SDC creation and DFT timing closure support.
    • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
    • TCL/PERL scripting for DFT automation, reporting, and debug.
    • Experience working across multiple ASIC technology nodes and complex product development cycles.
    • Familiarity with yield learning, diagnosis, and manufacturing test optimization.

    About USM Business Systems

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