Synopsys Inc

Interface IP Verification Engineer (Pre-Silicon) - 18381

Synopsys Inc$125K — $150K *
Information Technology
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • BSEE/MSEE with 5+ years of ASIC or SoC verification experience.
  • Deep expertise with SystemVerilog and UVM methodologies.
  • Strong knowledge of PCIe, CXL, DDR, and Ethernet protocols.
  • Experience in developing constrained-random and coverage-driven verification environments.
  • Proficient in debugging RTL and protocol compliance issues.
  • Familiar with industry-standard simulators like VCS or ModelSim.
  • Ability to collaborate across teams and independently drive initiatives.

Responsibilities

  • Own verification for Interface IP solutions including PCIe and DDR.
  • Architect and enhance UVM-based verification environments.
  • Define test plans from specification to product release.
  • Develop coverage-driven verification solutions using SystemVerilog.
  • Drive functional coverage closure and signoff activities.
  • Debug complex RTL and protocol-level issues.
  • Mentor engineers on verification methodologies and processes.

Benefits

  • Comprehensive health, wellness, and financial benefits package.
  • Professional development opportunities to support career growth.
Full Job Description
Descriptions & Requirements

Job Description and Requirements

The Opportunity

We're looking for an experienced ASIC Verification Engineer who is passionate about solving complex protocol challenges and delivering world-class Interface IP solutions.

In this role, you'll work on industry-leading PCIe, CXL, DDR, and Ethernet technologies that serve as foundational building blocks for AI accelerators, data centers, networking platforms, and next-generation SoCs. You'll collaborate with architects, design engineers, and verification experts to ensure the quality, performance, and reliability of technology used by leading semiconductor companies worldwide.

What You'll Do
  • Own verification of complex Interface IP solutions, including PCIe, CXL, DDR, and Ethernet technologies.
  • Architect, develop, and enhance scalable UVM-based verification environments and reusable verification IP.
  • Define verification strategies and test plans from specification review through product release.
  • Develop constrained-random, coverage-driven verification solutions using SystemVerilog and UVM.
  • Drive functional coverage closure and verification signoff activities.
  • Debug challenging RTL, protocol, and system-level issues while improving verification efficiency and automation.
  • Partner closely with architecture, RTL, firmware, and systems teams to identify issues early and ensure robust product quality while also mentoring engineers contributing to verification methodology improvements across the organization.

Why This Role Matters

The Interface IP you help verify will be integrated into some of the world's most advanced semiconductor products. Your work will directly impact the performance, reliability, and success of technologies powering:
  • AI and machine learning platforms
  • Cloud and hyperscale data centers
  • High-performance computing systems
  • Networking and communication infrastructure
  • Automotive and intelligent edge applications

What You'll Bring
  • BSEE/MSEE with at least 5 years of direct industry experience with proven experience verifying complex ASIC or SoC designs.
  • Deep expertise with SystemVerilog and UVM methodologies.

  • Strong protocol knowledge in one or more of the following areas:


PCI Express (PCIe), Compute Express Link (CXL), DDR Memory Interfaces, Ethernet
  • Experience developing constrained-random and coverage-driven verification environments.
  • Strong debugging and problem-solving skills spanning RTL, verification, and protocol compliance.
  • Experience with industry-standard simulators such as VCS, ModelSim, or similar tools.
  • Ability to independently drive technical initiatives while collaborating across geographically distributed teams.

Preferred
  • Experience with verification IP development, assertion-based verification and formal methodologies with knowledge of modern SoC architectures and high-speed communication interfaces.

What Success Looks Like
  • Deliver robust, high-quality verification solutions for complex Interface IP products.
  • Improve verification coverage, reusability, and execution efficiency.
  • Influence verification methodologies and best practices across engineering teams.
  • Drive successful product releases with exceptional quality standards.
  • Help develop the next generation of verification talent through technical mentorship and leadership.

The Team

You'll join a team of highly skilled verification engineers responsible for developing and verifying industry-leading Interface IP solutions. Working alongside experts in architecture, design, and verification, you'll tackle some of the semiconductor industry's most challenging technical problems while contributing to products deployed worldwide.

Rewards and Benefits

Synopsys offers a comprehensive package of health, wellness, financial, and professional development benefits designed to support you throughout your career.

#LI-SW1

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

About Synopsys Inc

Synopsys, Inc. is an American electronic design automation company that focuses on silicon design and verification, silicon intellectual property and software security and quality. Products include logic synthesis, behavioral synthesis, place and route, static timing analysis, formal verification, hardware description language (SystemC, SystemVerilog/Verilog, VHDL) simulators, as well as transistor-level circuit simulation. The simulators include development and debugging environments which assist in the design of the logic for chips and computer systems.
Learn more about Synopsys Inc
Size
16,361 employees
Market Cap
$48.6 billion
Industry
Net Income
$722.6 million
Founded
1986
5 Year Trend
+13.3%
Revenue
$3.8 billion
NASDAQ

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