Hardware Technical Program Manager

Efficient Computer

$200K — $240K *
Telecommunications & Hardware
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • B.S. in Electrical/Computer Engineering, Computer Science, or equivalent; M.S. or MBA is a plus.
  • 7+ years in semiconductor/hardware engineering or program management, with at least 2 full SoC/ASIC programs from concept through tapeout and silicon bring-up.
  • Fluency in chip design flow (RTL, verification, DFT, synthesis, physical signoff, GDSII).
  • Proven ability to create and defend detailed schedules with critical path analysis.
  • Track record of influencing teams and pushing for commitments effectively.
  • Strong communication skills for both technical and executive-level interactions.
  • Hands-on experience with program management tools (Jira, Confluence, MS Project) and EDA tools (Synopsys/Cadence/Siemens).

Responsibilities

  • Own the silicon schedule from architecture freeze through tapeout and production, aligned with customer requirements.
  • Drive the weekly execution cadence, maintaining a single source of truth for status and decisions.
  • Coordinate cross-functional handoffs between various teams throughout the design process.
  • Manage dependency chains crucial to program success, including IP delivery and PDK/library releases.
  • Run the tapeout checklist, ensuring all criteria are met before sign-off.
  • Work with supply chain for logistics related to silicon arrival and lab scheduling.
  • Provide early risk assessment and facilitate tradeoff discussions, documenting outcomes.

Benefits

  • Meaningful equity participation in the company.
  • Comprehensive healthcare benefits.
  • 401(k) retirement plan with employer matching.
  • Generous paid time off and holiday schedule.
  • Professional development and continuing education support.
Full Job Description
We are looking for a Hardware Technical Program Manager to own the program end-to-end - from architecture freeze through RTL, verification, physical implementation, tapeout, bring-up, and production release.

You will be the operational center of the program: building and defending the schedule, driving the critical path, surfacing risk early, and making the tradeoff conversations happen before they become slips. You'll work daily with architecture, RTL design, DV/emulation, DFT, physical design, package, firmware, and the foundry/IP vendor ecosystem. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities
Own the Program
  • Own the silicon schedule from architecture freeze through tapeout, bring-up, and production with the schedule informed by customer requirements and internal functional leads.
  • Drive the weekly execution cadence (program reviews, design reviews, tapeout readiness) and maintain a single source of truth for status, dependencies, and decisions.
Drive Cross-Functional Execution
  • Coordinate handoffs across architecture, RTL, DV/emulation, DFT, physical design, IP, package, and software
  • Manage the dependency chains hardware programs live and die on: IP delivery, PDK/library releases, EDA versions, and emulation capacity.
  • Run the tapeout checklist and signoff matrix (timing, power, IR/EM, DRC/LVS, DFT coverage, ECO closure, GDS handoff), holding owners to closure criteria.
  • Work with supply chain/logistics for: IP acquisition, silicon arrival, ATE/loadboard readiness, lab scheduling, bug triage, and ECO/respin decision support.
Manage Risk & Decisions
  • Surface risk early with mitigation options and schedule impact quantified - late IP, coverage shortfalls, convergence misses, foundry slot changes.
  • Facilitate PPA, schedule, and scope tradeoffs, and document what was decided, by whom, and why.
Coordinate Externally & Report Up
  • Interface with foundry, OSAT, IP, and EDA partners on deliverables, technology file releases, mask slots, and escalations; support export control/ECCN compliance with legal and operations.
  • Deliver crisp executive reporting - where the program stands, what's at risk, what decision is needed and by when - across distributed teams and time zones.
  • Track resource allocation and NRE/mask/license/prototype budgets against program needs.

Required Qualifications
  • B.S. in Electrical/Computer Engineering, Computer Science, or equivalent; M.S. or MBA a plus.
  • 7+ years in semiconductor/hardware engineering or program management, including at least 2 full SoC/ASIC programs taken from concept through tapeout and silicon bring-up.
  • Working fluency in the chip design flow: RTL, functional verification and coverage closure, DFT, synthesis, PnR, STA, physical signoff (DRC/LVS/IR/EM), GDSII handoff, and post-silicon validation.
  • Demonstrated ability to build and defend a bottoms-up schedule with critical path analysis and dependency mapping.
  • Track record influencing without authority - earning the technical credibility to push senior engineers on commitments and dates.
  • Strong written and verbal communication; able to run a room of principal engineers and an exec review with equal effectiveness.
  • Hands-on with program tooling: Jira, Confluence, MS Project/Smartsheet, and familiarity with the Synopsys/Cadence/Siemens EDA ecosystem.

Desired Qualifications & Experience Requirements
  • Prior hands-on engineering experience in design, DV, or physical design before moving to program management.
  • Experience on advanced or FinFET nodes (16/12/7nm or more advanced) and direct foundry engagement (TSMC preferred).
  • Familiarity with AI/ML accelerators, dataflow or novel compute architectures..
  • Experience managing emulation/FPGA prototyping programs and pre-silicon software enablement timelines.
  • Exposure to package/board co-design programs (FC-BGA, WLCSP) and OSAT coordination.
  • Experience with EVK/reference board programs and customer/FAE enablement schedules.
  • Familiarity with quality and compliance frameworks relevant to the target market (automotive, industrial, or security certifications).


We offer a competitive salary for this role, generally ranging from $200,000 to $240,000, along with bonus, meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

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