The RoleAs a Hardware Engineer, Architect, you will define the silicon and system microarchitecture for our custom unconventional compute platform-driving the architectural trade-offs that unlock a over traditional digital chips for
LLM and diffusion model inference.
You will lead the hardware/software co-design efforts to break the von Neumann memory wall. By translating transformer architectures (KV-cache management, attention mechanisms) and diffusion execution flows into custom mixed-signal compute tiles, memory hierarchies, and tile interconnects, you will set the blueprint for our hardware. Working closely with compiler, RTL, and analog teams, you will build performance models, establish microarchitectural specifications, and ensure our custom silicon delivers maximum throughput-per-watt on real-world generative AI workloads.
What You Will Own- Compute Architecture: Help define the architecture and microarchitecture of novel AI accelerator compute blocks: PE array design, datapath organization, and support for efficiency techniques such as sparsity exploitation and reduced-precision computation. The compute tile is the surface where Normal's research advantages have to show up in silicon, and you are one of the people responsible for making sure they do.
- Workload-to-Hardware Translation: Translate workload analysis and research findings into hardware specifications. Identify where architectural innovation creates the most leverage, define the structures that realize it, and produce microarchitecture documents unambiguous enough for RTL engineers to implement against. You work closely with them through implementation, not over the wall from it.
- Full-Stack PPA Tradeoffs: Reason across the full stack and defend PPA tradeoffs at every level. Move between algorithm-level workload behavior, memory hierarchy, on-chip interconnect, and physical design constraints. Make the call when the data is incomplete, and articulate why under scrutiny from our Systems Architect and the research team.
- ISA Co-Design: Partner with the compiler lead on ISA co-design. The programming model and the microarchitecture are defined together, and you are accountable for both sides meeting in the middle.
- Prototyping Strategy: Direct block-level pre-silicon validation. Decide which microarchitecture questions need to be answered, and the appropriate platform. Partner with our FPGA Design Engineers, who own implementation and bring-up, to de-risk decisions before tapeout. Work with the Systems Architect to make sure there are no gaps from block to System-level validation.
- Research Fluency: Stay current with the AI accelerator research landscape and be able to articulate clearly where Normal's approach differs from existing solutions and why that matters. This is a research-adjacent seat and you are expected to read, possibly publish, and not just consume.
What Makes You a Great Fit- A degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience. PhD welcome but not required; the bar is the work, not the credential.
- Substantial experience in architecture or microarchitecture of high-performance digital systems: AI accelerators, compute engines, or similarly complex logic. You have shaped and directed the structures inside a chip, not just consumed them from the outside.
- Fluency moving between algorithm-level analysis and hardware specification. You can read a profile of a workload and translate it into datapath widths, pipeline stages, and area/power estimates without losing the thread on either side.
- Experience with simulation-driven architecture. You have used cycle-accurate or analytical models to make and defend design decisions before RTL exists, and you know which questions each tool can answer and which it cannot.
- Familiarity with quantization and reduced-precision approaches for inference and their implementation implications. You understand the cost of a bit at the hardware level, not just the model level.
- Experience writing microarchitecture specifications and working closely with RTL engineers through implementation.
- Proficiency in Python or C++ for performance modeling and analysis, and familiarity with SystemVerilog or equivalent RTL.
- Comfort operating in an environment where the architecture is actively being discovered alongside the work. You do not need the answer to be already known to make progress on it.
