General Summary:
Looking for an experienced Emulation Engineer to manage, build, and launch verification jobs on hardware emulation platforms (e.g., Veloce, Palladium, ZeBu). You will work closely with design and verification teams to accelerate pre-silicon validation and ensure high-quality RTL delivery.
Minimum Qualifications:
• Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 4+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 3+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
PhD in Electrical Engineering, Computer Science, Computer Engineering, or related field and 2+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• 2+ years of experience with high-performance microprocessor design.
Responsibilities
- Set up, configure, and maintain emulation platforms (e.g., Veloce) for design bring-up and regression runs
- Compile and partition RTL designs for emulation, resolving synthesis and mapping issues
- Develop and maintain job scripts, infrastructure, and automation for launching and monitoring emulation runs
- Collaborate with DV engineers to port testbenches and verification environments to the emulation platform
- Debug emulation targets using Angel debug monitor, including semihosting for I/O and diagnostics during early bring-up
- Manage job scheduling and resource allocation across shared emulation hardware
- Track and report emulation run results; triage failures and escalate blockers
- Maintain version-controlled flows and scripts using Git
Required Skills
- Proficiency in SystemVerilog (RTL and/or testbench)
- Strong Git usage: branching, merging, managing flows across teams
- Hands-on experience with at least one emulation platform (Veloce, Palladium, ZeBu, or similar)
- Angel debug monitor - experience with the ARM Angel semihosting protocol for early-stage target bring-up, host-target
communication, and low-level diagnostics
- Understanding of emulation compilation flows (partitioning, clock domain handling, memory modeling)
- Scripting skills: Python, Tcl, or Shell for job automation and flow management
- Familiarity with UVM-based verification environments
Nice to Have
- Experience with SystemVerilog DPI or transactor-based emulation interfaces
- Background in FPGA synthesis or logic equivalence checking
- Knowledge of CDC (clock domain crossing) analysis and constraints
- Experience with LSF, Slurm, or similar job schedulers
- Familiarity with embedded operating systems (e.g., Zephyr, FreeRTOS, embedded Linux) and their bring-up on emulated or FPGA-based
platforms
Pay range and Other Compensation & Benefits:
$154,000.00 - $231,000.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
