You will execute the design, layout, bring-up, and qualification of the boards and SoMs that make our seeker run: FPA and image-sensor interface, GPU SoC / SoM carrier, high-speed digital and low-noise analog signal chains, shared-memory data plane between sensor and compute, power architecture from missile bus to detector bias rails, and the low-level firmware that brings it all up. This is a hands-on role for an engineer who can take a design from blank schematic to first-light bring-up to a low-latency CUDA pipeline running on an SoM in days, not months, and who thinks about manufacturability and second-source risk before the first prototype is built.
What You'll Do- Develop and bring up mixed-signal boards centered on a GPU SoC or SoM (NVIDIA Jetson/Orin, Qualcomm, NXP, or similar): high-speed image-sensor interface, low-noise analog chain, power conversion, and missile-bus IO.
- Architect and implement the high-speed image-sensor interface (LVDS, MIPI CSI-2, CameraLink, SLVS-EC, SerDes) end-to-end from sensor pinout to SoM ingest, including timing, signal integrity, and zero-copy DMA into GPU-accessible memory.
- Stand up the on-board compute path on GPU SoCs: CUDA pipelines, TensorRT inference, and shared-memory/zero-copy data movement from capture to inference, hitting hard latency and jitter budgets.
- Write low-level firmware, drivers, and bring-up tooling in Rust and Python: device-tree, sensor configuration, board diagnostics, automated bench tests, and the on-the-wire serialization layer (protobufs or equivalent).
- Execute schematic capture and PCB layout (Altium, Cadence, or KiCad), or partner with a layout designer when complexity warrants. Carrier-board design for the chosen SoM as required.
- Drive the power chain from missile bus to FPA bias rails (sequencing, low-noise LDOs, switching regulation, transient response, isolation), with component selection that bakes in cost, lead-time, second-source, and rad-tolerance from day one.
- Bring up boards on the bench (scope, logic analyzer, BERT, thermal imaging, rework iron) and chase low-latency, jitter-sensitive timing bugs to their physical root.
- Execute EMI/EMC qualification per MIL-STD-461 and environmental qualification per MIL-STD-810; partner with mechanical on conformal coating, staking, thermal interfaces, and survivability.
- Bake DFM and DFT in from the start: CM engagement, ICT/AOI, board-level test fixtures, and a clear path to volume.
Skills We're Hiring For- B.S. in Electrical Engineering, Computer Engineering, or related; M.S. preferred.
- 4 to 6 years of mixed-signal hardware and firmware bring-up experience, with responsibility for at least one board (ideally with an SoM carrier) from schematic through bench validation.
- Strong fundamentals across high-speed digital (signal integrity, controlled impedance), low-noise analog, and power conversion.
- Hands-on with high-speed image-sensor interfaces (LVDS, MIPI CSI-2, CameraLink, SLVS-EC, or SerDes) end-to-end from sensor to compute. Non-negotiable.
- Production CUDA experience: shipped real CUDA code, not dabbled. Reasons about kernels, memory layout, occupancy, streams, and host-device transfer cost; at the level needed to debug a stalled pipeline on an Orin.
- SoMs and shared-memory ecosystems (Jetson family or equivalent): zero-copy and unified-memory patterns, getting sensor data into GPU-accessible memory without copies you can't afford.
- Experience or strong willingness to work in Rust and Python for firmware, drivers, bring-up tooling, and low-latency host-side code.
- Hands-on TensorRT: model conversion, calibration, plugin integration, and deployment into a real on-board inference pipeline.
- Low-latency, jitter-sensitive applications: deterministic timing budgets, real-time scheduling, interrupt and DMA latency analysis.
- Schematic and PCB tooling proficiency (Altium, Cadence, or KiCad) with practical layout judgment. Comfortable on the bench (scope, logic analyzer, soldering iron, rework).
- AI-native working style: daily use of agentic coding tools (Claude Code, Codex, OpenCode, Kilo, or similar) for firmware, test-bench scripts, component selection, and schematic/layout review.
Bonus Points For- NVIDIA PVA, Qualcomm Hexagon, OpenCL, or other heterogeneous-compute runtimes beyond CUDA.
- Direct experience interfacing to IR detectors, focal-plane arrays, or ROICs (cooled or uncooled).
- Carrier-board design experience for a commercial SoM.
- High-volume or DFM experience: walked a board through CM bring-up at production rate.
- MIL-STD-461, MIL-STD-810, MIL-STD-1553, RS-422, or Ethernet-over-physical-layer qualification experience.
- Direct missile, munition, ISR, or aerospace-qualified hardware program experience.
Eligibility & Logistics Location: On-site at our Los Angeles, CA HQ; remote work is not available. Monthly weekend travel for test events and supplier engagements. Clearance: A clearance is not required for this position. Must be a U.S. Person.
