Internship Duration: 6 monthsHours: 40 hours per weekStart Date: Immediately (September 2026 /October 2026) Location: San JoseAbout The RoleWe are seeking a highly motivated and detail-oriented intern to join our team to contribute to SK Start-of-Art ECC (Error Correction Coding) IPs, which is the most critical part in ESSD.
Responsibilities- Perform work on running FPGA System and collecting data for performance
- Perform design database management in GIT
- Should be able to code RTL logic with Verilog syntax.
- Should be able to run simulation using Synopsys VCS.
- Should be able to debug simulation environment; compilation failure, simulation hang, simulation functional failure, etc.
- Should be able to communicate with designers, verification engineers, and other team for the correct solution.
Minimum Qualifications- Lab skill on windows software and hardware, and FPGA system.
- BS/MS degree (completed or in progress) in Electrical Engineering, Computer Engineering, or a related field.
- Must have proficiency in Verilog, SystemVerilog programming language.
- Must have good communication within co-working environments.
- Must have good work ethic, i.e. punctual on deadline, trustworthy commitment on assignment.
- Must be available to work 40 hours per week, Monday - Friday.
- 100% onsite commitment for a 6-month duration.
Preferred Qualifications:- Have a mindset on problem solving.
- Understand ASIC/FPGA workflow from concept to real silicon
- Scripting language skills such as Python, Perl, Tcl, etc.
- Experience in LDPC or Algebra code (BCH/RS) is a plus
COMPENSATION: $35/hr - $45/hr 
