Lattice Semiconductor

Dir, CAD Eng • R&D

Lattice Semiconductor$150K — $200K *
Consumer Technology
11 - 15 years of experience
Job Overview by Ladders

Qualifications

  • Master's in electrical engineering, computer engineering, or related field.
  • 15+ years in semiconductor design, with at least 7 in EDA methodology leadership.
  • Deep knowledge of RTL design, verification, synthesis, place & route, timing analysis, and sign-off methods.
  • Strong background in compute infrastructure and cloud-based design environments.
  • Proven ability to lead global teams and drive organizational change.
  • Excellent communication, negotiation, and strategic planning skills.

Responsibilities

  • Define and drive the long-term vision for EDA methodologies, flows, and infrastructure.
  • Architect and implement design flows for RTL-to-GDSII, verification, and physical design.
  • Oversee compute farms, license servers, and cloud integration for efficiency.
  • Develop a GenAI strategy for EDA design and methodology.
  • Collaborate with design, verification, CAD, and IT teams to align methodologies with project goals.
  • Evaluate and deploy EDA tools from major vendors; negotiate for optimal cost and performance.
  • Introduce automation and AI/ML-driven solutions to boost design productivity.
  • Build and mentor a high-performing team of CAD/EDA engineers.

Benefits

  • Opportunity to lead cutting-edge advancements in semiconductor design.
  • Access to modern cloud technology and infrastructure.
  • Collaborative environment with cross-functional teams.
  • Impactful role in shaping the future of EDA design methodologies.
  • Support for professional development and team-building initiatives.
Full Job Description
Responsibilities & Skills

Description: Director 6 CAD Design Engineering & EDA Infrastructure

Role Overview

The Director of EDA Design Methodology & Infrastructure will lead the development, deployment, and optimization of design automation flows, tools, and infrastructure across the organization. This role ensures that engineering teams have cutting-edge, scalable, and efficient methodologies to deliver complex semiconductor designs on time and with high quality.

Key Responsibilities
  • EDA Strategy: Define and drive the long-term vision for EDA methodologies, flows, and infrastructure to support advanced semiconductor design.
  • Methodology Development: Architect and implement design flows for RTL-to-GDSII, verification, physical design, timing closure, and sign-off.
  • Infrastructure Management: Oversee compute farms, license servers, cloud integration, and tool deployment to ensure scalability and efficiency.
  • GenAI Strategy for the EDA Design and Methodology
  • Cross-functional Collaboration: Partner with design, verification, CAD, and IT teams to align methodologies with project needs.
  • Tool Evaluation: Evaluate, benchmark, and deploy EDA tools from major vendors; negotiate with suppliers to optimize cost and performance.
  • Innovation Leadership: Introduce automation, AI/ML-driven flows, and cloud-native solutions to accelerate design productivity.
  • Team Leadership: Build and mentor a high-performing team of CAD/EDA engineers; foster a culture of technical excellence and innovation.
  • Process Standardization: Establish best practices, documentation, and training programs for design teams worldwide.
  • Risk Management: Identify and mitigate risks in tool flows, infrastructure, and project schedules.

Qualifications

  • Education: Master 27s in electrical engineering, Computer Engineering, or related field.
  • Experience: 15+ years in semiconductor design, with at least 7 years in EDA methodology leadership.
  • Technical Expertise: Deep knowledge of RTL design, verification, synthesis, place & route, timing analysis, and sign-off flows.
  • Infrastructure Knowledge: Strong background in compute infrastructure, cloud-based design environments, and license management.
  • Leadership Skills: Proven ability to lead global teams, manage vendor relationships, and drive organizational change.
  • Soft Skills: Excellent communication, negotiation, and strategic planning abilities.
Impact

This role is pivotal in enabling the company to design next-generation chips efficiently and competitively. By leading EDA methodology and infrastructure, the director ensures that engineering teams can innovate faster, reduce time-to-market, and maintain design quality at scale.

About Lattice Semiconductor

Lattice Semiconductor Corporation is an American manufacturer of high-performance programmable logic devices (FPGAs, CPLDs, & SPLDs). Founded in 1983, the company is headquartered in Portland, Oregon, and employs about 1,250 people. Lattice Semiconductor went public in 1989 and is traded on the NASDAQ stock exchange under the symbol LSCC. The company's products are used in communications, computing, industrial, automotive, and consumer markets.
Learn more about Lattice Semiconductor
Size
856 employees
Market Cap
$8.7 billion
Industry
Net Income
$47.3 million
Founded
1983
5 Year Trend
+3.8%
Revenue
$408.1 million
NASDAQ

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