Responsibilities - Define the DFT architecture of a multi-chip system SOC. involving all aspects of test design functions such as Scan, BIST, Memory Repair, BSD ( ACJTAG/DCJTAG).
- Proficiency in Synthesis design constraints. ( Ie SDC)
- Prior experience with Serializers/Deserilizers.
- Sound Proficiency in either Mentor /Synopsys Test Tools required. Proficiency is synthesis,
- Define and implement OCC. Exposure to advanced DFT techniques like LBIST and streaming preferred.
- Fluent in RTL level and Gate level simulation.
Qualifications- Knowledge using synthesis, DFT & Simulation CAD tools
- Familiarity with logic & physical design principles to drive low-power & higher-performance designs
- Fluency in scripting in some of these languages: Unix, Perl, Python, and TCL
- Good understanding of device physics and experience in deep sub-micron technologies 7nm or below.
- Prior Exposure to EMIB architectures and bridge is a plus.
- Knowledge of Verilog and System Verilog
- Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated
- Ability to work well in a team and be productive under aggressive schedules
- Prior experience of multiple tape out in deep submicron 7nm or below is required.
- Master's Degree or bachelor's degree in EE with a minimum of 15+ years of experience.
Why Join Us?At Eridu, you'll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
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The pay range for this role is:
195,000 - 250,000 USD per year (Saratoga, CA )
