Key Responsibilities:- Define the Physical Assembly of SOC. involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power.
- Proficiency in Synthesis design constraints (SDC).
- Design and Architect Top Level and block Level Floor planning of the entire SoC.
- Sound Proficiency in either Innovus or Synopsys Fusion Compiler required. Proficiency in synthesis, Floor planning Power Planning and Timing closure are required.
- Prior experience with large skew optimized clock tree designs like H-Tree preferred. Clock Grid exposure is a plus.
- Work extensively with Micro-architects to perform feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure.
- Develop physical design methodologies and customize recipes across various implementation steps to optimize PPA.
- Work with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as Timing, Power, EM/IR, PDV.
Qualifications- Master's Degree or bachelor's degree in EE with a minimum of 10+ years of experience.
- Knowledge using synthesis, place & route, analysis and verification CAD tools.
- Familiarity with logic & physical design principles to drive low-power & higher-performance designs.
- Fluency in scripting in some of these languages: Unix, Perl, Python, and TCL.
- Good understanding of device physics and experience in deep sub-micron technologies 7nm or below.
- Knowledge of Verilog and System Verilog.
- Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
- Ability to work well in a team and be productive under aggressive schedules.
- Prior experience of multiple tape-out in deep submicron 7nm or below is required.
Why Join Us?At Eridu, you'll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
The pay range for this role is:
210,000 - 250,000 USD per year (San Francisco Bay Area)
