Cadence Design Systems

DFT Design Engineer

Cadence Design Systems • $90K — $130K *
Austin, TX 78745In-Person
Information Technology
Less than 5 years of experience
Today
Be an Early Applicant
Job Overview by Ladders

Qualifications

  • 2-10 years of professional experience in SoC/ASIC Digital Design focusing on Design for Test (DFT)
  • Intimate knowledge of DFT insertion flows
  • Basic skills in scan chain insertion using synthesis or software tools
  • Experience with compression scan insertion, LBIST, and other scan technologies
  • Expertise in Automatic Test Pattern Generation (ATPG) for design test coverage
  • Debugging and analysis skills to improve fault coverage
  • Working knowledge of JTAG 1149.1/6, IEEE1500, and IEEE1687 standards
  • Prior experience with Cadence tools and flows is highly desirable

Responsibilities

  • Perform design for test (DFT) activities in SoC/ASIC environments
  • Insert scan chains and manage compression scan technologies
  • Conduct memory built-in self-tests (MBIST) to ensure reliability
  • Generate automatic test patterns to meet design coverage goals
  • Debug and analyze failures to enhance fault coverage
  • Verify ATPG testbenches and resolve simulation discrepancies
  • Collaborate with cross-functional teams including design and architecture groups

Benefits

  • Opportunity to work on cutting-edge ASIC/SoC projects
  • Collaborative and dynamic team environment
  • Engagement with internal and external stakeholders
  • Hands-on experience with advanced tools and methodologies
  • Potential for professional development and growth in the DFT field
Full Job Description
US citizenship Required

We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.

Requirements;
  • Prior 2-10 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
  • Should possess intimate knowledge of DFT insertion flows
  • Basic scan chain insertion using synthesis or other software tools
  • Experience in compression scan insertion, LBIST and other scan technologies
  • Intimate knowledge of memory build-in self-test (MBIST)
  • Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
  • Debug and Analysis of failures to improve fault coverage
  • Verification of ATPG testbenches and debugging root cause of simulation mis-compares
  • Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687
  • Knowledge of timing analysis and equivalency checks would be added bonus
  • US citizenship Required
  • Ability to work in collaborative team environment
  • Prior experience with Cadence tools and flows is highly desirable
  • Should be able to finish DFT tasks independently
  • Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems
  • Ability to work with stakeholders across cross-functional teams - Architecture, Design, Internal and External Customers
  • Self-driven and committed individual who can work in a fast-paced project environment

About Cadence Design Systems

Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Learn more about Cadence Design Systems
Size
9,300 employees
Market Cap
$43.9 billion
Industry
Enterprise Technology
Net Income
$590.6 million
Founded
2018
5 Year Trend
+10.5%
Revenue
$2.6 billion
NASDAQ
CDNS
* Ladders Estimates

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