Job Title: Design Verification Engineer

City: San Jose

State/Province: California

Posting Start Date: 9/17/26

Job Description:

Job Description

Design Verification Engineer

Location: San Jose, CA & Austin, TX - onsite

Job Summary:

We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.

Key responsibilities:

End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors

Understand vendor IP configurations and handle handshake with internal IP team

Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.

Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.

Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.

You may be a good fit if you have:

6 to 12 years of design verification experience

You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.

You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.

You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.

You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.

You collaborate naturally with cross-functional teams - from RTL design to software and emulation - and can clearly communicate technical insights.

Strong candidates may also have experience with:

Experience handling vendors and integration of IP/VIP's

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Mandatory Skills: VLSI Design For Testability - DFT.

Experience: 5-8 Years.

The expected compensation for this role ranges from $60,000 to $148,500 .

Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.

Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law.