Job Title: Design Verification Engineer City: Austin State/Province: Texas Posting Start Date: 6/4/26 Job Description: **Job Description** Key Responsibilities: Strong understanding of SV and UVM and good debugging skills. Understanding of AMBA protocols. Understand design specs and develop test plans based on functional and architectural requirements Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing Develop directed and random testcases, perform coverage analysis, and close functional/code coverage Debug simulation failures and work closely with RTL designers to resolve issues Execute regression runs, analyze results, and contribute to continuous improvements Integrate and run power-aware simulations, low power checks, and work with UPF/CPF as needed Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains Document test environments, testplans, and results for internal and external reviews Mandatory Skills: VLSI HVL Verification. Experience: 8-10 Years. The expected compensation for this role ranges from $80,000 to $158,000 . Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.