Job Title: Design Verification Engineer -Performance Modelling

City: Mountain View

State/Province: California

Posting Start Date: 7/10/26

Job Description:

Job Description

We need a DV engineer who has performance validation experience.
Key Responsibilities
• Develop, maintain, and enhance STL (Scenario/Test List) generation scripts and performance validation infrastructure.
• Monitor performance regression status and track key performance indicators (KPIs) across IP and subsystem level verification environments.
• Analyze regression failures and collaborate with IP, Design, and DV owners to drive issue resolution.
• Debug verification tests that fail to meet defined performance metrics and benchmark targets.
• Create, maintain, and update performance test plans, validation dashboards, and result tracking reports.
• Develop and execute SystemVerilog/UVM-based testcases and regression suites.
• Drive verification closure through regression analysis, debugging, and coverage tracking.
• Automate validation and reporting workflows using Python, Perl, or Shell scripting.
• Work closely with architects, designers, software teams, and validation engineers to ensure feature and performance signoff.
Required Qualifications
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 5+ years of Design Verification experience.
• Strong expertise in SystemVerilog and UVM.
• Experience developing and maintaining verification testbenches and regression environments.
• Strong debugging and root-cause analysis skills.
• Experience with verification planning, test development, and coverage closure.
• Proficiency in Python, Perl, or Shell scripting.
• Experience using industry-standard simulators and debug tools such as VCS, Xcelium, Questa, Verdi, or equivalent.
Preferred Qualifications
• Experience with performance validation, KPI tracking, or performance regression analysis.
• Experience with CPU, GPU, AI/ML, Multimedia, Interconnect, or SoC verification.
• Familiarity with performance benchmarking methodologies.
• Experience with emulation, FPGA prototyping, or post-silicon validation environments.
• Exposure to Formal Verification methodologies is a plus.
Key Skills
• SystemVerilog
• UVM
• Python / Perl / Shell
• Regression Debugging
• Verification Planning
• Coverage Analysis
• Performance Validation
• KPI Tracking
• Root Cause Analysis
• SoC/IP Verification
Tasks to be Owned
• Own and maintain healthy performance regression suites.
• Ensure performance KPIs are continuously tracked and reported.
• Drive timely debug and closure of performance-related test failures.
• Maintain accurate and up-to-date performance validation plans and dashboards.
• Partner effectively with cross-functional teams to achieve verification and performance signoff.

Mandatory Skills: VLSI HVL Verification.

Experience: 3-5 Years.

The expected compensation for this role ranges from $45,000 to $121,000 .

Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.

Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law.