Job Title: RTL Design Engineer
City: Mountain View
State/Province: California
Posting Start Date: 6/3/26
Job Description:
Job Description
Role Purpose
Role Purpose
Digital Design Engineering/RTL Design Services: • Architecture and microarchitecture of System on a Chip ("SOC") subsystems, Intellectual Property Functional Blocks ("IPs"), sub-IPs, modules, and library components • Digital design, using System Verilog and/or Verilog RTL, RTL generators (in Python), and/or high-level synthesis ("HLS"). RTL integration of SoC subsystems, IPs, sub-IPs, modules, and library components SoC-level integration • Support mapping of RTL on Zebu and HAPS for IP bring up and E2E validation • Design for low power and power intent design using Unified Power Format ("UPF") • Constraint development, synthesis, timing closure, and optimization of the design • Code quality checks, including but not limited to Linting, Clock Domain Crossing, Reset Domain Crossing • Debug and bug fixes
Mandatory Skills: VLSI Physical Place and Route.
Experience: 8-10 Years.
The expected compensation for this role ranges from $100,000 to $180,000 .
Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.
Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law.
