Design Verification Engineer, IP/SoC (Networking)

Procom

$90K — $120K *
Telecommunications & Hardware
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • 5+ years of experience in IP and SoC products
  • In-depth knowledge of System Verilog and UVM verification
  • Strong understanding of IP and SoC development methodology
  • Experience with EDA tools and scripting (Python, TCL, Perl, etc.)
  • Experienced in architecting design verification infrastructure
  • Knowledge of revision control systems like Git
  • Bachelor's degree in Computer Science, Engineering, or a related field

Responsibilities

  • Architect, design, implement, and verify Ethernet/networking IP for next-gen SoCs
  • Own UVM verification architecture and implementation for hardware IP and SoCs
  • Conduct performance and complexity trade-off analysis
  • Collaborate with architecture, design, and verification teams for timely, high-quality IP delivery
  • Produce detailed documentation for project phases
  • Develop directed and random verification tests
  • Debug test failures and resolve issues with engineers
  • Review and modify tests based on coverage metrics

Benefits

  • Hybrid work arrangement (3 days in office, 2 remote)
  • Opportunity to impact high-revenue product portfolios
  • Involvement in advanced technology across multiple sectors
  • Access to a dynamic, experienced R&D team
  • Focus on continuous improvement and innovation
Full Job Description
Design Verification Engineer, IP/SoC (Networking)

Permanent opportunity. Hybrid work arrangement in Ottawa (3 days in office/2 remote work)


Join a highly experienced R&D team dedicated to developing Intellectual Property (IP) for advanced microcontrollers and microprocessors. This team focuses on creating networking switch and network controller IP supporting the latest TSN standards, forming the networking foundation for next generation microcontrollers, processors, and switches. The IP developed by this team underpins a product portfolio generating billions of USD in annual revenue. The chips you help develop are likely found in the car you drive, the smart devices in your home, and the factories producing the goods you use.

This role sits within a central design organization developing products across Automotive, IoT, Networking, and Radio Frequency lines, spanning hardware engineering including architecture, IP, and full SoC design.

Job Description

We are seeking a highly motivated Design Verification Engineer with a relentless drive to excel and make a significant impact. This team offers innovative thinking, engineering expertise, and sustained market leadership in embedded processing. You will work with advanced platforms delivered to major players in the automotive, industrial, edge, and telecommunication markets, featuring multiple processing cores and high performance networking accelerators integrated on the same silicon chip.

Responsibilities
  • Architect, design, implement, and verify breakthrough Ethernet/networking IP to be integrated into next generation SoCs for automotive, industrial, and edge computing markets
  • Own the architecture, design, and implementation of UVM verification for hardware IP and System on Chip (SoC) products
  • Perform thorough trade off analysis on performance and complexity
  • Work closely with IP architecture, design, and verification teams on planning and execution to ensure the IP is delivered on time and with the highest quality
  • Produce quality documentation for all phases of the project, including detailed IP functional and implementation specifications
  • Build directed and random verification tests
  • Debug test failures to determine root cause, working with architects and design engineers to resolve defects and correct issues
  • Review functional and code coverage metrics, modifying or adding tests, or constraining random tests, to meet coverage requirements
  • Proactively drive continuous improvement in design and verification methodology

Job Qualifications
  • 5+ years of experience in IP and System on Chip (SoC) products
  • Thorough knowledge and expertise in System Verilog and UVM verification
  • Strong understanding of IP and SoC development methodology and proficiency in verification tools
  • Strong experience in EDA tools and scripting (Python, TCL, Perl, Makefile, Shell) used to build tools and flows for verification environments
  • Strong experience architecting and implementing design verification infrastructure and executing the full verification cycle
  • Experience with revision control systems like Git
  • Familiarity with hardware and software implementation trade offs
  • Focus on quality results with proven problem solving abilities
  • Algorithm development experience
  • Strong interpersonal, communication, and documentation skills
  • Dynamic team player
  • Bachelor's degree in Computer Science, Engineering, or a related field

Highly Desirable Skills
  • Familiarity with Formal and Functional Safety Verification
  • Knowledge of state of the art networking technologies, including TCP/IP protocols
  • Experience with data products such as routers, bridges, and switches
  • Security/cryptography experience

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