RTL 2 GDSII implementation of in-house IP and external customer designs Development, automation and maintenance of EDA flows and scripts for physical implementation

Develop TFM to optimize PPA for IP’s and Soft Controllers

PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, on TSMC, Intel, Samsung and Rapidus Foundries

Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools

Solid scripting skills including Python and Tcl.

Required skills –

Educational Qualification: MS/MTech/BE/ BTech  in Electronics from reputed institutes with 2 + years experience

Physical design experience in ASIC design environment

Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification

Should have excellent leadership, communication, analytical and problem solving skills

Should be self-motivated and good team player

The annual salary range for California is $87,500 to $162,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.