Qualifications

• Master's degree in Computer Engineering, Electrical Engineering, or related field.
• Minimum one year of relevant experience in electronic design or functional verification.
• Proficient in digital verification and documentation of verification processes.
• Skilled in planning verification environments and generating test plans.
• Experience in developing UVM based functional verification environments.
• Knowledge of SVA/System Verilog for protocol checker development.
• Familiarity with AMBA protocols for system-on-chip design integration.

Responsibilities

• Conduct research and development for electronic components and systems in EDA and semiconductor IP.
• Serve as the Functional Verification Engineer for DDR Memory Controller and Phy IP team.
• Execute functional verification of Cadence's DDR Memory Controller and Phy IP solutions.
• Enhance the existing functional verification environment by adding new features.
• Verify various customer configurations and provide support for related issues.
• Ensure compliance of designs with quality and technical requirements regarding functional and code coverage.
• Work includes some telecommuting flexibility.

Benefits

• Flexible telecommuting options.
• Opportunity to work on cutting-edge technology in EDA and semiconductor IP.
• Engagement with a collaborative verification environment.
• Professional development in advanced verification techniques.
• Involvement in direct customer support and tailored solutions.