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X In most instances, this position requires in-person interviews as part of the hiring process.Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
Austin, TX, USA; Mountain View, CA, USA.
Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with digital physical design implementation, including synthesis, Place and Route (PnR), and timing closure.
- Experience in high-performance, low-power physical design implementation or design convergence with industry standard synthesis, PnR and singoff tools.
Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Static Timing Analysis (STA), physical verification, or electrical checks using industry-standard tools.
- Experience working on high-performance CPU, GPU, or SoC block-level designs in advanced process nodes (e.g., 5nm or below).
- Proficiency in scripting with Tcl or Python for workflow automation and QoR analysis.
- Understanding of power grid design, EMIR constraints, and low-power implementation techniques.
About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $197000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities - Execute block-level physical design implementation from synthesis, Place and Route and design convergence via signoff checks.
- Analyze and resolve timing, congestion, and power issues to achieve optimal Power, Performance, and Area.
- Collaborate with cross-functional teams including RTL, Architecture, and DFT to align design constraints.
- Perform signoff activities, including Static Timing Analysis, physical verification, and power checks.
