Job Details:Job Description: About the Role
Join our CPU Design team and help develop the next generation of high-performance processors. In this role, you will contribute to the design, development, and optimization of custom digital and memory circuits that power advanced CPU architectures. Working alongside architecture, layout, verification, and design teams, you will apply circuit design fundamentals to deliver innovative solutions that improve processor performance, power efficiency, area, timing, and manufacturability.
As a CPU Design Engineer, you will participate in the design and verification of custom digital circuits, memory structures, and cache subsystems. You will collaborate with cross-functional teams to solve complex technical challenges, support product development milestones, and drive continuous improvements in design methodologies and automation flows.
What You’ll Do
Key responsibilities will include but not limited to:
- Design, develop, and optimize custom digital circuits for CPU and memory/cache subsystems.
- Perform circuit design, schematic entry, simulation, analysis, and verification of CPU building blocks.
- Analyze and optimize designs for power, performance, area (PPA), timing, reliability, and manufacturability objectives.
- Collaborate with CPU architecture, layout, physical design, and validation teams to deliver robust circuit solutions.
- Support development of Design-for-Test (DFT) structures, memory test methodologies, and characterization activities.
- Assist in identifying and resolving circuit design and performance issues throughout the development cycle.
- Contribute to automation, tool development, and methodology improvements that increase design efficiency and quality.
- Present technical findings, design results, and project updates to team members and stakeholders.
Behavioral traits that we are looking for:
- Strong analytical and problem-solving skills.
- Learning agility and technical curiosity.
- Effective collaboration and teamwork.
- Attention to detail and commitment to quality.
- Strong communication, initiative, and ownership.
Qualifications:Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Note:
Minimum Qualifications and Experience:
Bachelor's Degree in Electrical/Computer Engineering or any STEM related degree with 1+ years of experience in a high-tech company. Or a Master's Degree in the same filed with 3+ month of educational or work experience.
Your experience noted above must be in the following;
- Complementary MOS (CMOS) circuits design
- Digital logic and optimization
- Circuit design trade-offs for power, performance and area
- Very Large-Scale Integration (VLSI)
- Memory design experience
Preferred
- Low power implementation techniques
Job Type:College Grad
Shift:Shift 1 (United States of America)
Primary Location: US, Texas, Austin
Additional Locations:
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $91,150.00-172,860.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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