Job Details:Job Description:About the RoleAltera is seeking a highly experienced
Clocking Architect to lead the definition, design, and integration of clocking architectures for its next-generation FPGA and SoC devices. In this role you will own the end-to-end clocking strategy - from subsystem clock planning through full-chip integration - ensuring robust clock delivery, minimal skew, and compliance with all functional and DFT timing requirements across a diverse set of high-speed protocols.
The ideal candidate brings deep hands-on expertise in PCIe, High-Speed Memory I/O, ARM, Ethernet, and SerDes clocking domains, combined with mastery of SDC constraint authoring for both functional and DFT modes. This is a high-visibility, high-impact role with direct influence over silicon architecture decisions.
Key Responsibilities:Clocking Architecture & Full-Chip Strategy- Own and drive the complete clocking architecture for Altera's FPGA/SoC devices, including clock tree topology, domain partitioning, frequency planning, and PLL/DLL resource allocation.
- Define subsystem-level clocking plans aligned with chip-level power budgets, protocol timing margins, and physical implementation constraints.
- Establish clock gating policies, low-power clocking methodologies, and dynamic frequency scaling strategies.
- Deliver the clocking specification, clock architecture diagrams, and constraint management documentation as program-level deliverables.
- Collaborate with RTL, physical design, timing, and verification teams to ensure the clock architecture is correctly modeled and implemented across all design stages.
Protocol-Specific Clocking Expertise- PCIe (Gen4/5/6): Define REFCLK, PCLK, and spread-spectrum clocking (SSC) architectures; support SRIS/SRNS topologies and PCIe reset/power management clocking sequences.
- High-Speed Memory I/O (DDR5, LPDDR5, HBM2E/HBM3): Architect DFI clock, write leveling, read path, and DQS clocking to meet memory controller timing requirements.
- ARM Subsystems (Cortex-A/M/R, DSU, CMN Interconnect): Own core, peripheral, and AMBA bus clock hierarchies; ensure compliance with ARM's timing and power requirements.
- Configuration Interfaces (eSPI, SPI, JTAG, LPC): Define boot and configuration clock domains, including secure boot and JTAG test clock isolation.
- Ethernet (1G/10G/25G/100G/400G): Architect MAC, PCS, and PHY clock domains; support SyncE and IEEE 1588 Precision Time Protocol (PTP) clocking requirements.
- SerDes (PCIe, Ethernet, Custom High-Speed I/O): Define lane CDR, TX/RX PLL, and gearbox clocking; address reference clock distribution and jitter budgets for multi-lane interfaces.
ML/AI Accelerator Clocking- Architect clocking solutions for FPGA-based and SoC-integrated ML/AI inference and training accelerator pipelines, including matrix multiply units, systolic arrays, and vector processing engines.
- Define multi-frequency clock domain strategies for AI workloads: separate clock planes for compute fabric, memory subsystem (HBM/LPDDR), host interconnect (PCIe), and control path to maximize throughput and efficiency.
- Own clocking for high-bandwidth AI memory interfaces (HBM2E/HBM3, LPDDR5X) used in AI inference cards and data-center FPGA overlays, ensuring sub-picosecond jitter budgets at peak bandwidth.
- Support dynamic voltage and frequency scaling (DVFS) clocking architectures that adapt compute clock rates to AI workload demand and thermal headroom.
- Collaborate with AI IP and compiler teams to align clock domain boundaries with dataflow partitioning, pipeline stage timing, and latency requirements of ML models.
- Define clocking for on-chip AI accelerator interconnects (NoC, AXI streaming fabrics) and ensure CDC-clean handshaking between host, memory, and compute domains.
Clock Domain Crossing (CDC) Architecture & Verification- Own the full-chip CDC architecture plan: identify, classify, and document every asynchronous clock domain crossing from RTL inception through tape-out sign-off.
- Define synchronizer insertion strategies (2FF, 3FF, handshake, FIFO-based) appropriate to each crossing type, frequency ratio, and data hazard profile; establish metastability MTBF budgets per domain pair.
- Drive CDC structural and functional verification using industry-standard tools (Synopsys SpyGlass CDC, Cadence JasperGold CDC, Mentor Questa CDC); own CDC closure criteria and waiver review process.
- Author set_clock_groups, case_analysis, and false_path constraints in SDC to accurately model asynchronous relationships; validate that constraint intent matches RTL implementation.
- Establish CDC coding guidelines and review checklists for RTL designers; enforce rules via lint and CDC tool flows integrated into the design methodology.
- Lead CDC debug and root-cause analysis for functional failures attributable to domain crossings, including post-silicon correlation and errata investigation.
- Define CDC sign-off criteria per tape-out milestone; own the CDC waiver database and ensure all open items are resolved or risk-assessed before tapeout.
Timing Constraints - Functional & DFT- Author, own, and maintain comprehensive SDC constraints for functional timing closure across all clock domains, generated clocks, and interface IPs.
- Define and manage clock exceptions: false paths, multicycle paths, case analysis, and set_clock_groups for synchronous and asynchronous CDC domains.
- Develop DFT-specific clocking constraints for scan shift, scan capture, ATPG, MBIST, and LBIST operating modes.
- Architect On-Chip Clock Controller (OCC) strategies for scan clock control and support DFT engineers with test-mode clock mux insertion.
- Partner with STA engineers (Synopsys PrimeTime / Cadence Tempus) to drive timing closure and sign-off across all PVT corners.
Integration & Cross-Functional Leadership- Lead clocking architecture reviews with IP owners, SoC architects, physical design leads, and external IP vendors.
- Define clocking sign-off criteria for tape-out milestones and own the clocking checklist through tapeout.
- Mentor junior and senior engineers on clocking best practices, constraint methodology, and debug techniques.
- Represent the clocking team in design reviews, customer technical engagement, and Altera architecture planning sessions.
What Altera Offers- The opportunity to shape clocking architecture for the world's most advanced programmable logic devices.
- A collaborative, engineering-first culture with direct visibility into chip architecture decisions.
- Comprehensive benefits: medical, dental, vision, 401(k) with company match, and paid parental leave.
- Flexible hybrid work model and dedicated professional development investment.
- Access to Altera's world-class EDA infrastructure, IP libraries, and advanced process node programs.
Salary RangeThe pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$187,000 - $270,700 USD Qualifications:Minimum Qualifications- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 12+ years of industry experience in physical design, SoC/FPGA design, or clocking architecture, with silicon tape-outs at 7nm or below.
- Proven ownership of full-chip and subsystem-level clocking architecture on high-complexity SoC or FPGA devices.
- Deep expertise across PCIe (Gen4/5/6), DDR5/LPDDR5/HBM, ARM CoreLink/CMN, Ethernet (1G-400G), Configuration interfaces, and SerDes clocking.
- Demonstrated experience architecting clocking for ML/AI accelerator silicon: multi-frequency compute/memory/interconnect clock planes, DVFS, and HBM/LPDDR5X integration.
- Expert-level CDC architecture ownership: full-chip CDC planning, synchronizer strategy, metastability analysis, and end-to-end CDC sign-off.
- Proficiency with CDC verification tools (SpyGlass CDC, JasperGold CDC, Questa CDC) including waiver management and RTL coding guideline enforcement.
- Expert-level SDC constraint authoring and validation using Synopsys PrimeTime and/or Cadence Tempus.
- Comprehensive DFT clocking experience: scan, ATPG, OCC, MBIST, LBIST, and associated SDC methodology.
- Experience with low-power design methodologies (UPF/CPF) and their interaction with clock gating and multi-voltage power domains.
Preferred Qualifications- FPGA or programmable logic background with understanding of fabric clocking resources (PLLs, global/regional clock networks, GCLK/RCLK routing).
- Experience with clocking for hard IP subsystems within FPGA SoC devices (e.g., HPS, PCIe hard blocks, memory controllers).
- Background in AI/ML FPGA overlay design: knowledge of tensor/matrix engine clocking, dataflow pipeline clock domain partitioning, and AI inference latency optimization through clock architecture.
- Experience with formal CDC verification and model checking (VC Formal) for synchronizer correctness proofs.
- Familiarity with PLL/DLL characterization, frequency margining, jitter budget analysis, and SSC validation.
- Knowledge of IEEE 1500, P1687 (IJTAG), and their clocking implications for embedded DFT instrumentation.
- Experience with multi-die/chiplet clocking architectures (UCIe, BoW, AIB) and die-to-die CDC management.
- Scripting proficiency in Tcl and/or Python for constraint automation, CDC report parsing, and custom analysis flows.
- Familiarity with Intel/Altera FPGA architecture (Stratix, Agilex product families) a significant advantage.
Job Type: Regular
Shift:Shift 1 (United States of America)
Primary Location:San Jose, California, United States
Additional Locations: 
