Pay rate range - $95/hr. to $100/hr.
Onsite - Bellevue, WA OR Boston, MA

Description:
A Chip Design Engineer focuses on the design, verification, and physical implementation of digital silicon, and the support of training environment ( "gym ") development across chip design domains.
They play a hands-on role in validating that gym tasks accurately represent real front-end design, verification, and physical/back-end work at Client.
Chip Design Engineers use a variety of industry-standard tools to review and assess tasks for realism, define the skill bar for correct solutions, and consult with gym-building teams.
This involves RTL design review, assertion-based verification, understanding of the RTL-to-GDSII flow and how to identify where tasks diverge from real engineering practice.

Required Skills:
Digital ASIC or SoC design experience across front-end, verification, and physical/back-end flows.
Hands-on proficiency with SystemVerilog for design and verification.
Assertion-based verification using SystemVerilog Assertions (SVA).
Operation of Synopsys tooling across the design flow (e.g., VCS, Design Compiler, IC Compiler II / Fusion Compiler, PrimeTime).
Ability to explain the reasoning and tradeoffs behind design decisions, not just correct outcomes.
Customer service and partner with gym-building teams.
Manage relationships and projects with model training teams and domain experts.
Continuously improve and extend task realism and quality standards.
Detail-oriented.
Verbal and written communication skills.
Strong organizational skills, ability to work independently, and maintain professionalism under pressure.

Additional Skills:
Full RTL-to-GDSII flow familiarity.
UVM-based verification environments.
Static timing analysis, low-power design (UPF), and DFT.
Preferred tooling: Synopsys and industry-standard EDA suites.
An Electrical Engineering, Computer Engineering, or equivalent technical degree and 10+ years of relevant experience is required.