Application close date:

Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide.

We are seeking aSenior-level Mixed-Signal / Custom Digital IC Designerto develop, simulate, characterize, and deliver timing models for custom analog-digital interface circuits. This role is responsible for creating high-qualityLiberty.libtiming modelsand related collateral for custom digital and mixed-signal interface blocks used in complex integrated circuits.

The ideal candidate has strong transistor-level circuit design and simulation experience, deep understanding of digital timing concepts, and hands-on experience characterizing custom cells or interfaces forsetup, hold, clock-to-Q, recovery/removal, pulse-width, propagation delay, slew, load, and PVT variation. This person will work closely with analog designers, digital implementation engineers, STA engineers, verification engineers, and physical design teams to ensure that custom mixed-signal interfaces are accurately represented in digital timing flows.

This role is well suited for a designer who is comfortable operating at the boundary betweenanalog/mixed-signal design, custom digital design, static timing analysis, and library characterization.

Special Mentions:

- Relocation provided

- Travel expected up to 10% of the time

- Interviews will include a technical assessment

- This role is based on site in San Diego (preferred), CA Or Cupertino, CA; A temporary remote work exception is approved while our San Diego sites are being developed.

Responsibilities include but are not limited to:

• Generate and maintainLiberty.libmodelsfor custom digital and analog-digital interface circuits:
  • Define and characterize timing arcs including input-to-output delay, clock-to-Q delay, setup and hold constraints, recovery and removal timing, minimum pulse-width constraints, enable/disable timing, tristate or conditional timing arcs, where applicable.
  • Characterize timing over relevant PVT corners, input slew ranges, output load ranges, and extracted parasitic conditions
  • Model pin capacitance, transition behavior, leakage, dynamic power, and related Liberty attributes as needed.
  • Validate generated.libfiles against transistor-level simulation results and downstream STA behavior.
  • Ensure.libcompatibility with digital implementation and signoff tools such as PrimeTime, Tempus, Innovus, Fusion Compiler, or equivalent.
• Perform SPICE-level characterization:
  • Build, debug, and maintain transistor-level simulation testbenches for custom interface circuits.
  • Run SPICE or FastSPICE simulations using tools such as Spectre, HSPICE, Eldo, FineSim, XA, or equivalent.
  • Develop measurement methodologies for setup/hold extraction, propagation delay, clock-to-Q delay, transition time, minimum pulse width, recovery/removal checks, and metastability-sensitive timing behavior
  • Perform simulation across PVT and parasitic-extracted views.
  • Analyze waveform behavior and identify root causes of timing anomalies, non-monotonicity, race conditions, glitches, contention, or metastable behavior.
  • Create automated characterization flows using scripting languages such as Python, Tcl, Perl, shell, or SKILL.
• Cross-functional integration
  • Collaborate with digital design, STA, verification, physical design, and analog/mixed-signal teams.
  • Support integration of custom.libmodels into synthesis, place-and-route, timing signoff, and verification flows.
  • Review STA results to confirm that custom interface timing is represented correctly.
  • Work with layout and physical design teams to understand and model parasitic impact.
• Documentation and methodology development
  • Document characterization methodology, simulation conditions, measurement definitions, and modeling assumptions.
  • Produce timing characterization reports and validation summaries.
  • Define standard practices for custom cell and mixed-signal interface characterization.
  • Create reusable characterization templates, testbenches, and automation infrastructure.
  • Mentor junior engineers in custom timing characterization, Liberty modeling, and SPICE-based validation.

Minimum Qualifications:

• BS or MS in Electrical Engineering, Computer Engineering, or related field, with 7+ years of relevant experience.
• Significant experience in custom IC design, mixed-signal design, standard-cell characterization, or digital timing methodology.
• Hands-on experience with transistor-level simulation using SPICE-class tools.
• Strong understanding of CMOS digital circuit design, including:
  • Inverters
  • Combinational logic
  • Latches
  • Flip-flops
  • Transmission gates
  • Clocked logic
  • Reset/set structures
• Strong understanding of timing concepts including:
  • Setup time
  • Hold time
  • Clock-to-Q delay
  • Propagation delay
  • Slew/load dependence
  • Recovery/removal timing
  • Minimum pulse-width checks
• Experience generating or validating Liberty.libfiles.
• Experience with PVT-based characterization and corner analysis.
• Ability to analyze SPICE waveforms and debug unexpected circuit behavior.
• Scripting experience in Python, Tcl, Perl, shell, SKILL, or similar.
• Ability to work effectively with analog, digital, verification, STA, and physical design teams.
• Strong communication skills.

Preferred Qualifications:

• Experience with Cadence Virtuoso, ADE Explorer/Assembler, Spectre, and related analog/mixed-signal design tools.
• Experience with library characterization tools such as:
  • Cadence Liberate, Synopsys SiliconSmart, Solido Characterization Suite
  • custom in-house characterization flows
• Experience with STA tools such as:
  • Synopsys PrimeTime
  • Cadence Tempus
• Experience with extracted-netlist simulation using DSPF, SPEF, or post-layout parasitic views.
• Experience with level shifters, synchronizers, comparators, custom clocking circuits, and clock-domain-crossing interfaces.
• Experience modeling circuits with analog-dependent timing behavior, metastability, hysteresis, or threshold-crossing behavior.
• Experience in advanced CMOS technology nodes.
• Familiarity with reliability and robustness analysis, including:
  • Aging
  • EM/IR
  • Supply noise
  • Mismatch
  • Monte Carlo analysis
  • Local variation
• Experience creating Verilog, Verilog-A, SystemVerilog, or specify-block models to accompany Liberty timing models.
• Familiarity with digital implementation flows including synthesis, place-and-route, timing closure, and signoff.

Base Pay Range for:

Other site ranges may differ

Benefits

• Benefits include:  Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
• Stock Options for all regular employees (working at least 20 hours/week)
• Paid Time Off:  Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
• Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the companys intent to reward individual contributions and enable them to share in the companys results, or other factors at the companys sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation. Please check with your recruiter for more details.