Job Details:Job Description:The Role and Impact Join Intel's cutting-edge mixed-signal IP development team as a Senior Mixed Signal Design Engineer. This role combines analog circuit design expertise with specialized focus on static timing analysis for next-generation mixed-signal systems. You'll drive timing closure across analog-digital interfaces while supporting comprehensive design verification activities that directly impact Intel's industry-leading products.
Working in a collaborative environment with analog designers and system architects, you'll leverage tools like Cadence ADE to execute simulations, debug complex testbenches, and optimize circuit performance. This position offers significant opportunities to enhance verification methodologies and contribute to behavioral modeling initiatives that accelerate silicon success.
If you are passionate about analog circuit design combined with mixed-signal verification (especially static timing analysis), and you thrive in a fast-paced, collaborative setting, we encourage you to apply.
Key Responsibilities:Static Timing Analysis & Design Closure - Lead static timing analysis (STA) execution for mixed-signal designs, ensuring robust timing closure across analog-digital interfaces
- Drive timing optimization and constraint development for complex mixed-signal systems
Analog Circuit Design & Verification - Execute analog circuit design tasks including simulation setup, testbench development, and schematic optimization using Cadence ADE
- Perform comprehensive mixed-signal verification encompassing analog simulations, behavioral modeling, and timing analysis
- Analyze simulation results for power, performance, and reliability compliance
Debug & Problem Resolution - Investigate and resolve complex issues in analog testbenches and mixed-signal simulations
- Root-cause analysis of pre-silicon design challenges with systematic corrective action implementation
- Collaborate across disciplines with analog designers, digital architects, RTL teams, and physical design engineers
Methodology Enhancement - Develop behavioral models to improve simulation accuracy and efficiency
- Advance verification flows and methodologies supporting evolving mixed-signal design requirements
- Contribute to automation initiatives using scripting and emerging AI technologies
Core Competencies - Strong analytical and problem-solving skills, alongside effective team collaboration capabilities.
- Good communication skills
Qualifications:SPECIAL NOTE - Intel is in the process of securing office space in the greater metropolitan area of Toronto, Ontario. This office will serve as your assigned work location in the future. Once the site is operational, your position will follow Intel's hybrid work model, which currently requires on-site presence at least four days per week. Until the office is ready, you will be classified as a remote employee and will be working virtually from the greater metropolitan area of Toronto, Ontario.
The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates
Minimum Qualifications - Bachelor's degree in Electrical or Computer Engineering or in a STEM related field with 2+ years of industry experience
- 2+ years of experience with mixed signal verification and driving methodology changes and initiatives.
- 2+ years of experience in scripting languages such as Python for automation purposes.
Preferred Qualifications- Post Graduate degree in Electrical or Computer Engineering or in a STEM related field.
- Experience working within mixed signal systems like SerDes or PLLs.
- Experience with static timing analysis and analog circuit designs.
- Experience with Cadence ADE for running simulations and debugging testbenches.
- Experience with script development and automation using AI.
- Experience with mixed-signal design principles, including interfaces between analog and digital domains.
- Strong analytical and problem-solving skills, alongside effective team collaboration capabilities.
- Experience with analog behavioral modeling (Verilog-A, SystemVerilog, etc.) is a plus
Join us to be at the forefront of innovation and help shape the technology that powers the future. Apply today and take the next step in your engineering journey with Intel.
Job Type:Experienced Hire
Shift:Shift 1 (Canada)
Primary Location:Virtual Canada
Additional Locations:Business group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Annual Salary Range for jobs which could be performed in Canada
CAD 129,740.00-183,170.00
Salary range dependent on a number of factors including location and experience.Work Model for this RoleThis role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.
