Deliver high-performance C++ applications for a cutting-edge hardware emulation framework. Collaborate with RTL Designers, Compiler Developers, and Software Engineers to enhance RISC-V core IP and improve software development productivity and debugging.

Lead the charge in verifying complex cache-coherent interconnect subsystems, defining comprehensive strategies and methodologies to enhance verification quality while mentoring engineers and collaborating across multiple technical teams for successful integration.

Drive verification excellence by leading strategy for a scalable cache-coherent interconnect subsystem, orchestrating collaboration across teams to ensure quality and reliability in high-performance CPU and SoC designs.

Lead the charge in defining and executing verification strategies for a scalable cache-coherent interconnect subsystem in high-performance CPU and SoC platforms, while driving quality and cross-team collaboration.

Drive innovation in CPU and interconnect IP design while enhancing RISC-V adoption. Collaborate in a fast-paced environment to create high-quality, configurable hardware solutions that meet diverse application needs with cutting-edge methodologies.