Lead high-performance CPU frontend verification, collaborating with architecture and design teams to innovate solutions. Drive strategies across verification planning, execution, and debug, enhancing methods and quality throughout the organization.

Shape the future of CPU-subsystem power-management verification by leading the planning, execution, and technical strategy to ensure quality and resiliency in complex SoC environments, directly impacting data-center-grade functionality and integration.

Drive innovation as you design advanced CPU and interconnect IP, leveraging RISC-V architecture to accelerate time-to-market and enhance hardware configurability within a dynamic engineering environment.

Drive innovation by architecting advanced hardware solutions in CPU design and interconnect IP, contributing to the acceleration of RISC-V adoption across various industries. Collaborate in a dynamic environment to enhance and deploy high-performance technologies.

Unlock potential by designing industry-leading CPU and interconnect IP, enhancing performance and configurability in a dynamic environment. Collaborate and innovate to accelerate the adoption of RISC-V architecture across diverse applications.