Working on state-of-the art Fetch Unit architecture design serving both general purpose as well as AI processing element needs; Experience with branch prediction algorithms / instruction fetch design of high performance microprocessors.

Working on Execution Unit; Logic design experience with state of the art deep submicron technologies specifically low power design techniques; Experience with Arithmetic Unit (ALU) logic design with emphasis on high speed processor pipeline designs.

Working with a small team to implement, debug, and verify Prodigy’s internal and external buses. Building the infrastructure needed to bringup and debug the various components in FPGAs and silicon.

Working on high performance L2 Cache unit serving the needs of state-of-the art AI processing elements. Experience with cache controller designs, understanding of cache coherency protocols, cache hierarchy.

Responsible for implementation of ultra-high performance and low power data processing chip. Work with RTL designers to achieve PPA goals and suggest appropriate tradeoffs.