About the RoleYou own verification end to end for a first-of-its-kind chiplet. As a founding hire you define the methodology before there's RTL to verify - this role is on the critical path, and getting the coverage strategy and regression infrastructure right early is the single biggest schedule lever we have.
What You'll Own- The full DV strategy: verification plan, coverage model (functional + code), UVM architecture, and signoff criteria from block to full-chip.
- Stand up regression/CI infrastructure and nightly runs before design hands over first RTL.
- Verification of the in-house engines against an algorithmic golden model, with programmable error injection and error-pattern coverage.
- Hardware-assisted verification: bring up and own the emulation / FPGA-prototyping methodology.
- UCIe VIP and compliance, link-training, loopback, lane-repair scenarios, bit-exact transparency and more.
- Performance and throughput verification.
- UVM register verification, firmware co-simulation, and boot flows on the MCU subsystem.
- Mixed-signal co-simulation - verifying the digital front end against behavioral models of analog/mixed-signal blocks.
- Gate-level and low-power (UPF) verification as part of signoff.
- Lead and grow the DV team (across FEC, UCIe, MCU, datapath, and full-chip).
Required- 10+ years ASIC/SoC verification, with team leadership on at least one complex SoC from plan to tapeout.
- Proven leadership verifying large, complex digital SoCs / subsystems, including interconnect fabric and full-chip closure.
- Deep UVM/SystemVerilog; coverage-driven verification; constrained-random methodology.
- Hands-on with hardware-assisted verification - emulation (e.g., Palladium/Veloce) and/or FPGA prototyping (e.g., HAPS/Protium).
- Comfortable with mixed-signal verification (Verilog-AMS or SV real models).
- Regression/CI at scale (grid, triage automation), and rigorous coverage closure.
Preferred- High-speed SerDes, PAM4, or FEC/coding (Reed-Solomon) verification experience.
- UCIe, PCIe/CXL, Ethernet, UALink or comparable die-to-die / link-layer VIP and compliance experience.
- NIC Cards, Ethernet/IB Switches, Cache-coherency verification (multi-core / coherent fabric).
- Low-power/UPF and gate-level simulation methodology.
- Performance-verification methodology.
- Formal verification for control/interlock logic; portable-stimulus.
What We Offer- Competitive salary commensurate with experience
- Comprehensive benefits package including health, dental, and vision
- Professional development opportunities and certification support
- Access to cutting-edge technology and cloud platforms
- Collaborative work environment with cross-functional teams
