Well-rounded expertise in ASIC verification processes
In-depth knowledge of ASIC architecture and verification flow
Proficient in low-level programming (C/C++/Assembly)
Familiarity with ASIC verification environments (UVM, System Verilog)
Understanding of industry-standard interfaces and Verilog debug tools
Experience with constrained random verification methods and functional coverage
Strong interpersonal skills and a collaborative mindset
Responsibilities
Drive pre-silicon RTL verification of complex SOCs
Review specifications and develop test attributes and coverage plans
Align with design and micro-architecture teams on functional goals
Conduct test plan reviews and develop block/full chip tests
Triaging failures and verifying gate-level functionality
Run regressions and track bugs effectively
Work independently while integrating efforts with cross-functional teams
Benefits
Competitive salary package
Stock options for every employee
Comprehensive healthcare, dental, and vision benefits
401k plan
Catered lunch with healthy snacks and beverages
Generous paid vacation and holidays
Relocation assistance and reimbursement options
Free parking and transportation incentives
Full Job Description
Job Description
ASIC Verification Description
Here, you will be working at the heart of our chip design efforts; where we are collaborating with all disciplines and making a critical impact in getting functional products to millions of customers quickly.
What does our SOC DV team do? Well, we're verifying high throughput complex SOCs, and you'll get to drive the pre-silicon RTL verification of the full chip.
We are working daily to ensure the quality of the SOC by working closely with the team in reviewing specifications, developing attributes, tests & coverage plans, defining methodology & test benches.
We have to closely align with our design & micro-architecture teams to understand the functional & performance goals of the design.
You'll have to stay abreast with design specs by conducting test plan reviews, developing block/full chip tests & triaging failures.
Your collaborative approach will be necessary in driving the verification efforts in your specific area. You'll also support gate level functional verification, run regressions, handle bug tracking, analyze code & functional coverage, etc.
Do you enjoy working independently too? You will get plenty of time to work on your tasks while still aligning closely with the project goals, and our multi-functional engineering efforts.
Qualifications
We're looking for candidates who are well-rounded in all aspects of verification.
Knowledge of ASIC architecture/design & in-depth knowledge of asic verification flow.
You will thrive by demonstrating your expertise with low-level programming of complex computer systems in C/C++/assembly.
Being already familiar asic verification environments such as UVM and System Verilog will come a long way with us.
Apply your knowledge of industry standard interfaces and your deep understanding of Verilog, Verilog simulator, and debuggers.
You should have a thorough understanding of the constrained random asic verification process, functional coverage, code coverage, assertion methodology & philosophy.
Even better if you also have knowledge of formal, hardware acceleration.
You should be an outstanding teammate with excellent interpersonal skills and the desire to take on diverse challenges.
Additional Information
Perks + Benefits:
Competitive salary package
Stock options for every employee
Healthcare + dental + vision (Free for employee/heavily discounted for family)
