TOP Design Verification Engineer Intern

SK Hynix Memory Solutions America

• $72K — $93K *
San Jose, CA 95123In-Person
Technical Services
Less than 5 years of experience
Today
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Job Overview by Ladders

Qualifications

  • Bachelor's or Master's in Electrical Engineering or related field
  • Experience in Digital IC Design and Verification
  • Proficient in Windows and Linux environments
  • Scripting skills in Python or Perl
  • Familiar with System Verilog, UVM, and C/Assembly coding
  • Experience using Perforce and Confluence
  • Knowledge of UCIe, CPU architecture, NAND protocols, and AI productivity tools is a plus

Responsibilities

  • Analyze the Microarchitecture of the SOC TOP and outline verification requirements
  • Modify the Test Bench for SOC TOP level testing
  • Develop or adjust Test Cases to validate SOC functionalities
  • Debug issues and file bug reports for designers
  • Ensure testing meets Functional and Toggle coverage criteria

Benefits

  • Gain hands-on experience in a cutting-edge technological field
  • Opportunity to work in a collaborative, innovative environment
  • Exposure to industry-standard tools and technologies
  • Contribute directly to significant projects
  • Build professional networks in semiconductor engineering
Full Job Description
Internship Duration: 6 months

Hours: 40 hours per week

Start Date: Immediately (September 2026 /October 2026)

Location: San Jose

Responsibility :
  • Study the Microarchitecture of the Design (SOC TOP) and list the Verification Requirements
  • for testing.
  • Modify the Test Bench for the SOC TOP level testing.
  • Create/Modify Tests Cases to test the functionalities of the SOC.
  • Debug & identify the issue & file bug reports to Designer.
  • Testing to meet the Coverages (Functional, Toggle) criteria.


Minimum requirements :
  • A Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE) or a related field is required.
  • Digital IC Design & Verification experiences.
  • Work in Windows and Linux environment.
  • Python or Perl scripting experience.
  • Experience in System Verilog, UVM, C/Assembly coding
  • Experience in Perforce and Confluence.
  • Familiarity with UCIe, CPU architecture, NAND protocols, and AI productivity tools is a plus.


COMPENSATION: $35/hr - $45/hr
* Ladders Estimates

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