Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
- 12 years of experience in Physical Design, Custom Digital Circuit Design, or Custom Layout.
- Experience delivering GDS for advanced nodes.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience in custom digital design and low power design techniques.
- Experience with custom design tools and methods.
- Experience in Electromagnetic Modeling (EM) and its impact on physical layout (Inductors, T-lines).
- Experience in Co-Packaged Optics (CPO) physical implementation.
- Ability to build strategic goals for the intersection of AI-driven layout and traditional custom design.
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As the Lead Architect for Google's custom back-end solutions for high-speed internal connections, you will set the design standards for our custom silicon. You will ensure our physical design methods can support data speeds of 1.6T and above while maintaining high manufacturing reliability and performance. You will create the design framework for our future hardware, solving complex engineering challenges in the latest manufacturing processes.
Responsibilities- Define the global back-end and custom Physical Design methodology, driving the transition to automated Analog and Mixed-Signal (AMS) flows and "Layout-Aware" design.
- Lead full custom digital circuit design at the transistor level optimized for low power.
- Evaluate and de-risk new process features in GAA (Gate-All-Around) nodes (e.g., Backside Power Delivery, Buried Power Rails) for high-speed analog use cases.
- Drive the long-term Roadmap for Area and Power density, ensuring our PHYs remain the most efficient in the industry.
- Act as the primary liaison with foundries to optimize Design for Manufacturing (DFM) and maximize yield for massive TPU-scale chips.
US: $240000 - $334000 (USD) 25% bonus target equity benefits
Learn more about benefits at Google .
