Astera Labs

Tech Lead, Digital Design Engineer

Astera Labs • $138K — $165K *
Telecommunications & Hardware
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's degree in Electrical Engineering required; Master's preferred.
  • 3+ years' experience in complex SoC/silicon development for networking applications.
  • Ability to manage multiple tasks and prepare for customer meetings with little supervision.
  • Proactive, entrepreneurial mindset with a strong focus on customer needs.
  • Authorized to work in the US and available to start immediately.

Responsibilities

  • Develop micro-architecture and front-end circuit designs for high-performance network controllers.
  • Perform RTL design, synthesis, and IP integration for SoC products.
  • Conduct block-level verification and ensure timing closure.
  • Utilize digital design tools from Synopsys and/or Cadence for project implementation.
  • Engage in silicon bring-up and debugging processes.

Benefits

  • Encouragement of diverse applicants and inclusive work environment.
Full Job Description
Job Description

We are looking for Senior Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.

Basic Qualifications:
  • Strong academic and technical background in electrical engineering. A Bachelor's degree in EE is required, and a Master's degree is preferred.
  • +3 years' experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
  • Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
  • Authorized to work in the US and start immediately.

Required Experience:
  • Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
  • Proven front end design skill - architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
  • Block level ownership from architecture to GDS.
  • Experience with Synopsys and/or Cadence digital design tools/flows
  • Knowledge of design for test (DFT)
  • Familiarity with UVM based design verification
  • Silicon bring-up and debug experience
  • Small-geometry CMOS (≤28nm) design

Preferred Experience:
  • Scripting with Python or other equivalent programming languages.
  • Development/support for PCIe or Ethernet Switch products.


We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About Astera Labs

Astera Labs is a semiconductor company that designs and develops purpose-built connectivity solutions for data-centric systems. The company's portfolio of products includes system-aware semiconductor integrated circuits (ICs), boards, and intellectual property (IP) that are used in data center servers, storage, and networking equipment. Astera Labs' products are designed to improve the performance, latency, and power consumption of data-centric systems. The company was founded in 2018 and is headquartered in Santa Clara, California.
Learn more about Astera Labs
Size
51 employees
Industry
Net Income
-$3 million
Founded
2018
Revenue
$5 million
NASDAQ

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