The application window is expected to close on: 09/29/2026
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
This position requires that you live within commuting distance of our San Jose, CA office and commute to the office at least 4-5 days per week.
Your ImpactWe are seeking a qualified Signal and Power Integrity Engineer to help us develop our next generation ASIC packaging to help define, design and verify ASIC packaging to be deployed in a range of Cisco platforms.
Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
Minimum Qualifications - Bachelor's degree in Electrical Engineering and 6+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 3+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 1+ years of relevant signal and power integrity related work experience.
- High-Speed Design & Theory: Expertise in high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
- SI/PI Simulation Proficiency: Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
- Layout Review & Physical Validation: Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and crosstalk mitigation.
- Circuit Analysis: Working knowledge of SPICE for circuit-level analysis, signal modeling, and performance validation.
Preferred Qualifications- Skilled in articulating ideas and technical concepts to diverse audiences, both verbally and in writing.
- Experience with high-bandwidth memory (HBM) or high-speed memory interface SI.
- Experience with die-to-die interfaces (UCIe or proprietary).
- Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging.
- Working knowledge of Vector Network Analysis.
- Basic knowledge of IBIS.
