12+ years of experience in high-speed interconnect technologies, including retimers and coherent optics.
Previous role as System Architect, Chief Architect, or Principal Systems Engineer on a product with 100G/lane or higher.
Proven track record with direct authorship of product and silicon specifications for shipping products.
Strong fluency in PAM4 link training, FEC, and telemetry at the specification level.
Familiarity with traceability tools such as DOORS, JAMA, or their equivalents.
Responsibilities
Own the SoC and Product Specification stack for a 1.6T retimer SoC and related AEC products.
Author and maintain normative specifications for various teams to execute against.
Define standards scope across multiple industry standards like IEEE, OIF, and JEDEC.
Represent architecture in negotiations on specifications with hyperscaler and strategic customers.
Involved in establishing qualifications and commitments for test points, telemetry, and thermal envelope.
Benefits
Opportunity to lead high-impact projects in cutting-edge technology.
Direct involvement in cross-functional collaboration across teams.
Role in negotiations with major industry players in high-speed interconnects.
Exposure to the latest standards in the field and significant influence on product direction.
Full Job Description
Own the SoC and Product Specification stack for a 1.6T retimer SoC and the AEC product it enables, at 224G/lane PAM4.
You will author and maintain normative specifications (SHALL/MUST/SHOULD/MAY language with REQ-ID traceability) that RTL, firmware, software, SI/PI, manufacturing, qualification, and customer engineering teams execute against.
You will represent architecture in hyperscaler and strategic platform customer specification negotiation, including qualification test point, FEC telemetry, CMIS vendor-page, and thermal envelope commitments. Required:
12+ years in shipping high-speed interconnect (retimer, gearbox, PHY, AEC, AOC, coherent optics, SerDes-centric networking silicon).
Prior System Architect, Chief Architect, or Principal Systems Engineer role on a shipping 100G/lane or higher product.
Direct authorship of at least one product spec and one silicon spec on a shipping product.
PAM4 link training, FEC, and on-die telemetry fluency at the specification level.
