Micron Technology

Staff SoC Physical Verification Engineer, HBM

Micron Technology • $120K — $150K *
Richardson, TX 75080In-Person
Information Technology
8 - 10 years of experience
Reposted Today
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Job Overview by Ladders

Qualifications

  • 5-7 years of experience in physical verification for advanced-node SoCs or memory designs.
  • In-depth knowledge of physical verification methodologies including DRC, LVS, and DFM.
  • Familiarity with tools like Calibre or IC Validator, with experience in rule deck development.
  • Understanding of RTL-to-GDS flows and their physical verification implications.
  • Strong communication skills to facilitate cross-functional collaboration.

Responsibilities

  • Lead full-chip and hierarchical physical verification sign-off, including DRC, LVS, and ERC.
  • Debug foundry-qualified rule decks, manage waivers, and ensure compliance with specifications.
  • Conduct reliability checks for ESD, latch-up, and connectivity integrity across power domains.
  • Perform checks for manufacturability at advanced nodes, including CMP and metal fill.
  • Support parasitic RC extraction and correlate results with post-silicon evaluations.
  • Develop and enhance physical verification automation and flow optimization scripts.
  • Implement AI/ML approaches in physical verification and PPA optimization.

Benefits

  • Choice of comprehensive medical, dental, and vision plans tailored to family needs.
  • Income protection programs for illness or injury-related work absence.
  • Paid family leave to support personal obligations.
  • Robust paid time-off program along with designated paid holidays.
Full Job Description
As a Physical Verification Engineer, you will be a key technical contributor within the Heterogeneous Integration Group (HIG), responsible for defining, executing, and driving sign-off quality physical verification flows for next-generation HBM logic die and memory-centric SoCs. You will work across physical design, design rule development, EDA tool teams, foundry interfaces, and product engineering teams to deliver industry-leading, tape-out-ready silicon under aggressive schedule, quality, and reliability constraints. This role combines full-chip physical verification ownership - including DRC, LVS, ERC, and DFM - with deep collaboration across implementation and silicon bring-up, ensuring design integrity from layout through first silicon.

Responsibilities will include, but are not limited to:
  • Lead end-to-end physical verification sign-off for full-chip and hierarchical designs, including Design Rule Check (DRC), Layout Versus Schematic (LVS), Electrical Rule Check (ERC), Physical Electrical Rule Check (PERC), antenna checking, and Design for Manufacturability (DFM).
  • Execute and debug foundry-qualified rule decks, manage waivers, and drive clean closure while ensuring compliance with advanced-node foundry requirements.
  • Perform reliability verification across multiple power domains, including electrostatic discharge (ESD), latch-up, electromigration, floating nets, and connectivity checks.
  • Run density, metal fill, and chemical mechanical polishing (CMP) checks to ensure yield-aware manufacturability at 3 nanometer and below.
  • Perform parasitic resistance-capacitance (RC) extraction and support correlation of physical verification results with post-silicon measurements.
  • Develop, maintain, and optimize physical verification flows, automation, and regression infrastructure using Python, Tcl, Perl, or similar scripting languages.
  • Drive adoption of machine learning (ML) and artificial intelligence (AI)-based physical verification and power-performance-area (PPA) optimization tools.
  • Partner with physical design, custom layout, computer-aided design (CAD), register-transfer level (RTL), product engineering, EDA, and foundry teams, including direct interface with TSMC, from design kick-off through tape-out readiness and sign-off decision gates.
Minimum Qualifications:
  • Strong experience with full-chip or block-level physical verification for advanced-node system-on-chip, memory, or heterogeneous integration designs.
  • Deep hands-on expertise in physical verification methodologies, including DRC, LVS, ERC, PERC, DFM, antenna, and reliability sign-off.
  • Experience using industry physical verification tools such as Calibre, IC Validator (ICV), Pegasus, or similar, including rule deck development or customization.
  • Working knowledge of full RTL-to-GDS implementation flows, including place-and-route, extraction, and their impact on physical verification outcomes.
  • Ability to drive verification closure through strong cross-functional communication in a global engineering environment.
Preferred Qualifications:
  • Experience with high-bandwidth memory (HBM), DRAM, or memory-centric system-on-chip physical verification, including multi-die, chiplet, or 2.5D/3D integration.
  • Background in GPU, CPU, or high-performance accelerator physical implementation at advanced process nodes with aggressive sign-off and tape-out schedules.
  • Familiarity with foundry design rule documents, front-end-of-line (FEOL) and back-end-of-line (BEOL) rules, and advanced design for manufacturability best practices.
  • Exposure to post-silicon failure analysis, yield learning, or layout-based debug with correlation between physical verification results and silicon behavior.
  • Master's or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience, with 10 or more years of relevant industry experience including mentoring engineers and driving physical verification methodology improvements.


As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

About Micron Technology

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Learn more about Micron Technology
Size
43,000 employees
Market Cap
$53.7 billion
Industry
Manufacturing & Automotive
Net Income
$2.9 billion
Founded
1978
5 Year Trend
+8.6%
Revenue
$22 billion
NASDAQ
MU
* Ladders Estimates

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