Position OverviewWe are seeking an experienced Silicon Photonics Designer to join our SiPh team. In this role, you will own the end-to-end design, simulation, layout, and characterization of passive silicon photonic components-including edge couplers, grating couplers, and hybrid/directional couplers-targeting a high-performance co-packaged optics system for artificial intelligence Inference applications. You will work directly with renowned foundry partners and cross-functional teams in VLSI, packaging, systems, and testing to bring photonic designs from concept to production-ready silicon.
LocationSan Francisco Bay Area. Full-time onsite position.
Key Responsibilities- Design, simulate, and optimize passive silicon photonic building blocks: edge couplers (inverse tapers, spot-size converters), grating couplers (1D/2D, chirped/apodized, dual-polarization), and hybrid/directional/multimode-interference (MMI) couplers for compact PIC designs.
- Develop waveguide routing, splitters, polarization splitters/rotators (PSR), crossings, and other PIC sub-elements with explicit attention to insertion loss, return loss, bandwidth, polarization dependence, and process variation tolerance.
- Conduct FDTD, eigenmode expansion (EME), and circuit-level simulations using Ansys Lumerical, Synopsys Optsim, or equivalent tools; perform tolerance and process-corner analysis to ensure robust yield across foundry runs.
- Implement PIC layouts using Cadence Virtuoso, KLayout, or script-based parametric design flow, generate DRC-clean GDS for submission to foundry, including DRC/LVS sign-off, design review, and mask data preparation.
- Manage and drive tapeout processes with mainstream SiPh foundries, or equivalent silicon photonics PDKs
- Interface directly with foundry process engineers to negotiate design rule waivers, understand process corners, and resolve integration challenges throughout the design cycle.
- Define and execute design-of-experiments (DOE) test chip strategies to characterize process sensitivities and close the loop between simulation and measurement results.
Qualifications- M.S. or Ph.D. in Electrical Engineering, Photonics, Applied Physics, or a closely related discipline
- 3+ years of hands-on silicon photonics design experience in an industry setting (or equivalent depth of graduate research with demonstrated tapeout and measurement record).
- Proven expertise in designing passive silicon photonic components: edge couplers, grating couplers, directional/hybrid couplers, waveguides, and splitters on SOI platforms.
- Proficiency with photonic simulation tools: FDTD, BPM, FDE, CMT, and EME solvers (Ansys Lumerical Suite, Synopsys Rsoft, Photon Design, or equivalent) and circuit-level simulation.
- Demonstrated PIC layout experience using Cadence Virtuoso, KLayout, and/or Python-based parametric layout frameworks (GDSFactory, IPKISS, or similar) for GDS generation.
- Familiarity with electro-optic device design (Lasers, MZM, ring modulator, Ge photodetector) to enable holistic PIC integration.
- Experience with at least one commercial silicon photonics foundry PDK and tapeout flow (TSMC, GlobalFoundries - GF Fotonix /AMF, Tower, AIM Photonics, or equivalent).
- Programming proficiency in Python and/or MATLAB for simulation automation, data analysis, and statistical evaluation of device performance.
- Working knowledge of datacom or coherent transceiver link architectures and system-level optical specifications.
- Experience with coherent PIC design elements: IQ modulators, optical hybrids (90° hybrid), polarization splitters/rotators, and balanced detector integration.
Preferred Skills- Direct foundry interface experience with silicon photonics platforms-including DRC/LVS sign-off, OPC coordination, and MPW/dedicated wafer shuttle management.
- Full tape-out ownership: concept 1 simulation 1 layout 1 DRC clean 1 tapeout 1 wafer receipt 1 measurement 1 design iteration.
- Strong knowledge on high-speed optoelectronics device design and measurement
- Hands-on optical measurement skills: coupling loss/insertion loss characterization, swept-wavelength spectral measurements, polarization-dependent loss (PDL) measurements.
- Familiarity with SiN photonics platforms (low-loss, broadband) for edge coupler or wavelength-routing applications.
- Good knowledge on wafer backend process and optical packaging: lensed-fiber or FAU edge-coupling assembly, active alignment, and fiber attachment processes for photonic modules.
- Exposure to co-packaged optics (CPO) architectures, flip-chip or die bonding of III-V laser sources, or heterogeneous photonic integration.
- Experience with automated measurement scripting (Python GPIB/VISA frameworks, automated wafer-level or die-level test stations).
- Publications, patents, or conference presentations (OFC, ECOC, SPIE Photonics West) demonstrating silicon photonics design contributions.
What We OfferThis is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on a game-changing technology at the intersection of photonics and AI as part of a collaborative and brilliant team. You1ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.
BenefitsJoin a team that invests in your future and your well-being. At Neurophos, we offer:
- 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
- Unlimited PTO. No rigid vacation banks, just a focus on delivery.
- 401(k) matching and stock option opportunities to ensure our success is your success.
- Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
- Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don1t.
