The Role

As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open-standard RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Responsibilities

• Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.

• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.

• Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.

• Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.

• Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.

• Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.

Requirements

• BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.

• 3+ years of design experience.

• Academic or professional experience with CPU RTL design. 

• Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.

• Strong software engineering skills/background, including:

  • Object-oriented, aspect-oriented, and particularly functional programming

  • Test-driven development, particularly ability to write adaptive unit tests

• Attention to detail and a focus on high-quality design.  Good verification principles, SVA, and coverage.

• Ability to work well with others and share the belief that engineering is teamwork.

Nice-to-haves

• Experience with Scala/Chisel, Bluespec, or some other language/DSL for generating configurable hardware via software.

• Knowledge of RISC-V instruction set architecture.

• Expertise in out-of-order processor micro-architecture, design, and verification in one or more of the following areas: load-store unit, coherent caches, cache prefetching, virtual memory MMU/TLBs.

• Familiarity with Git/Github, Jira, Confluence.

Pay & Benefits

Consistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. 

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! 

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.