Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in physical design, with experience in leading the full-chip or complex subchip implementation (e.g., from RTL2GDSII, including key stages like floorplanning, place and route, and timing closure) of high-speed ASICs in process technologies.
- Experience in Python, Tcl, or Perl scripting.
Preferred qualifications:- Master's degree or PhD in electrical engineering, computer engineering, or computer science, with an emphasis on computer architecture.
- Experience in technical leadership, managing execution schedules, mitigating risks, providing status updates, and driving cross-functional collaboration with internal teams and external vendors to improve flows.
- Experience in Cadence Innovus, Synopsys DP, Mentor Calibre, STARRC, with a strong understanding of foundry technology files, rule decks, physical signoff, and 2.5D/3D IC packaging.
- Strong understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
- Excellent communication skills to articulate complex technical challenges and solutions.
About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Staff Physical Design Engineer, you will lead the end-to-end physical design implementation of complex silicon projects. You will drive technical excellence from RTL to GDSII, oversee critical sign-off closures, and foster cross-functional collaboration to optimize power, performance, and area (PPA). Beyond project execution, you will serve as a technical leader, influencing methodologies, guiding vendor engagement, and ensuring predictable delivery through effective planning and communication.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $279000 (USD) 20% bonus target bonus equity benefits
Learn more about benefits at Google .
Responsibilities- Oversee the physical design implementation of complex blocks, subchips, and top-level designs, ensuring technical excellence and project success.
- Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
- Partner with internal teams (RTL, DFT, methodology, package) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
- Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
- Own and plan the physical design execution schedule, actively communicating status and risks to management.
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