Staff Engineer, IP Design (ASIC)

SK hynix memory solutions America Inc.

$130K — $180K *
Telecommunications & Hardware
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • 8+ years of ASIC design experience with a focus on PCle logic integration.
  • Proficient in debugging RTL using Verdi/VCS and task automation via Python or Perl.
  • Skilled in SystemVerilog/Verilog for RTL development and microarchitecture.
  • Knowledgeable in Clock Domain Crossing (CDC), timing closure, and synthesis flows.

Responsibilities

  • Design and verify high-speed interfaces for NVME or Chiplets.
  • Lead cross-functional teams through the RTL development and silicon bring-up process.

Benefits

  • Medical, dental, and vision insurance.
  • Life insurance coverage.
  • 401(k) company match.
  • Access to cafeteria and onsite gym.
  • Supportive environment encouraging career growth.
Full Job Description
About the Team

You will join the System on Chip (SoC) Design Team at SK Hynix memory solutions America, a group dedicated to delivering best-in-class controllers for high-performance SSDs. This team spans the full design cycle-from micro-architecture and RTL design to timing closure and tapeout readiness-enabling next-generation enterprise and AI data center storage solutions. As a Staff Engineer, you will own critical High speed interface IP, drive methodology improvements (such as AI-assisted design flows), and mentor engineers to ensure first-pass silicon success.

Responsibilities
  • Design and verification of the high speed interface for next generation storage subsystem for NVME or Chiplet.
  • Drive team efforts with multi-function teams from RTL development through silicon bring-up.

Minimum Qualifications
  • 8 years of experience in ASIC design and deep knowledge in the design and integration of PCle logic.
  • Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
  • Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition.
  • Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows.

Preferred Qualifications
  • Experience in PCle(Gen4/5/6) architecture in TLP/FLIT pipelines, flow control, ordering rules, and performance tuning.
  • Proven experience with Link training, power state(L0/L0P/L1/L2), error handling (AER).
  • Experience with cross-functional leadership, driving efforts with software/system teams from RTL development through silicon bring-up.
  • Good plus to have experience in AI Assist design flow.

Education
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

REGARDING COMPENSATION:

SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.

The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.

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